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Created with Raphaël 2.2.010Oct8126Sep23191817131130Aug2827262220141387531Jul3029251918121110532128Jun272624201918171431May29282220171615148763130Apr262318151211853227Mar2522212019181514131287426Feb222120191514138654131Jan291615148320Dec191814131211107654327Nov131287SELFOUR-161: Merge Page_Remap with Page_Mapia32, boot: Create device frames for unused RAMkernel: attempt direct switch on set priox86: avoid -Waddress-of-packed-membermcs: Don't rollback time when not reschedulingseL4Config.cmake: Add FORCE to KernelSel4Archaarch64: Move tpidrro_el0 from vcpu to tcb contextKernelIRQReporting: Change reserved IRQ reportingpc99,CMake: Move configs to x86 dirCMake: Mark config options as advancedCMake: Add KernelHardwareDebugAPIUnsupportedgcc.cmake: Configure ccache in toolchain filearmv8,CMake: Split generic timer, counter accessarmv8: expand generic timer user-level accessCMake: Add FindseL4.cmake modulecmake: Only include cmake files for selected archcmake: Add SEL4_CONFIG_DEFAULT_ADVANCED variableCMake: Invoke configuration files to build kernelCMake: Error if toolchain file changesCMake: Possibly set toolchain file automaticallyaarch64: allow access to memory below physBasealyons-aarch64-…alyons-aarch64-addraarch64: update fpsimd_HWCapTest for ARMv8.2setup.py: depend on 'pyyaml', not 'pyaml'setup.py: add Python dependency on libarchive-cRevert "setup.py: add Python dep[] on libarchive"hifive: Real time clock operates at 1MHzmcs: enable MCS for riscvmcs: Boot RISC-V with scheduling control & contextmcs: RISC-V uses 39-bit addressing in stuctures.bftrivial: spelling of the word 'canonical'mcs: Update size constants for RISC-Vmcs: fastpath_reply_recv reply argument for RISC-Vmcs: Timeout fault and reply for RISC-Vmcs: add mcs capability variants for riscvmcs: libsel4 for RISC-Vmcs: Select additional registers for RISC-Vmcs: Implement timer functions for RISC-Vmcs: Remove timer init and reset from RISC-Vriscv: Fix rollover when reading time in 32-bitriscv: Relocate read time to header