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Created with Raphaël 2.2.012Feb1110530Jan2922201410623Dec191817161311106229Nov282726222120191817161412530Oct252423221411108126Sep23191817131130Aug2827262220141387531Jul3029251918121110532128Jun272624201918171431May29282220171615148763130Apr262318151211853227Mar2522212019181514131287426Feb222120191514138654131Jan291615148320Dec191814131211Specify the C compiler in a variable for user lvlmcs-smp: tcb affinity modification bugtrivial: Bugfix, use the correct config macrox86: Fix printf typo in apic_init()nomadeel/fix_pr…nomadeel/fix_printf_typoARM: Add support to flush L1 cachesriscv32 does not support huge pagesarm,SMP: Refactor irq_t structure for smpDocument internal machine/interrupt.h interfacetrivial: Remove duplicate function prototypestrivial: Remove unused ipiBroadcast functionupdate non-mcs sabre clockimx31: Add missing DTS entry for the EPIT2 timerFix MCS timer for KZMFix TX1 clock timerMove vcpu_switch into Arch_switchToThreadaarch64: fix FAR_EL1 width in writeFARaarch64: fix MRS/MSR in writeELR_EL1manual: improve discussion of Recv and Waitmanual: rework introduction of system callstrivial: arm: Improve object method docsaarch64: Fix seL4_ARM_PageDirectory interface docRISCV: Added stdout-path to hifive dtsRevert "Cache FPU enable state on all platforms"Revert "trivial: use global machine/fpu.h (arm)"Revert "Ensure that FPU state enables fpu on aarch32"unify userSize type declarationsMake padding word-size independentName anonymous structsriscv: Fetch faulting instructionsriscv_hypriscv_hypbitfield: Extend the code field for UserExceptiontrivial: Change the default HE version to 0.3trivial: sstratch -> sscratch for RISCV HEtrivial: Fix rebase errorriscv: Add RISCV HE v0.4 supportriscv: Add an option to track the RISCV HE versionriscv: SMPify the VTimer coderiscv_hyp: Read PC before setting SPRV bittrivial: Fix merge errorriscv: Add experimental RISCV-HE supporttrivial: Fix style