Switched appropriate naming conventions.
Was using the aarch64, have switched to aarch64 names.

TIPDRURW -> tpidr_el0
TPIDRURO -> tpidrro_el0
TPIDRPRW -> tpidr_el1

Switch TLS register on aarch32 from TPIDURO (tpidrro_el0) to tpidr_ro so
that it can be written to from user-land.

Thread ID registers tpidr_el0 have been added to the user context for
aarch32 and aarch64.

Only the thread ID that is writeable from EL0 is saved in the TCB and
saved/restored on context switch.

Thread IDs that are only changed within a VM (the read-only thread ID
for exception level 0 and the thread ID for exception level 1) are
stored in the VCPU and saved and stored as part of VM enable/disable.

Thread IDs that are only changed with VMs have been separated out into
hypervisor code.

The globals frame no longer serves its original purpose of informing a
thread of its IPC buffer address, and instead as a virtual
implementation of thread ID registers.

TLS_BASE virtual register is replaced with FS_BASE and GS_BASE virtual
registers.

The FS_BASE and GS_BASE virtual registers are moved to the end of the
context so they need not be considered in the kernel exit and entry
implementation.

Removed tracking of ES, DS, FS, and GS segment selectors on kernel entry
and exit.

ES and DS are clobbered on kernel entry with the RPL 3 selector for a
DPL 3 linear data segment.

FS is clobbered on exit with the RPL 3 selector for the DPL 3 segment
with FS_BASE as the base. This is done on exit to reload the value from
the GDT.

GS is clobbered on exit with the RPL 3 selector for the DPL 3 segment
with GS_BASE as the base. This is done on exit to reload the value from
the GDT.

Kernel entry and exit code is refactored, simplified, and improved in
light of the above changes.

x64: update verified config to use fsgsbase instr

The verification platform for x64 relies on the fsgsbase instruction.

This removes the assumption that each platform sotres the IPC buffer
address in a platform-specific register. The IPC buffer address is
instead stored in a thread-local variable in libsel4 which must be
initialised by the runtime.

Instead of processing each platform CMake file during the arch's
config.cmake file, we process all of the platform CMake files first.
This is primarily motivated by wanting to move platform configuration
into a config file that is processed via a -C argument to the initial
build initialisation command.

Now a platform config is responsible for setting the kernel architecture
and it's own platform/arch specific config settings. Where previously a
platform was chosen in an arch specific way via either setting
KernelARMPlatform or KernelX86Sel4Arch or KernelRiscVPlatform, a
platform can now be set by KernelPlatform. In cases where a platform may
further parameterise its configuration it is free to choose its own
config options to query. Platforms that support multiple seL4
architectures should use KernelSel4Arch to query this.  Platforms that
provide sub platforms such as exynos5 and subplatforms exynos5250,
exynos5410 and exynos5422 can be selected by specifying
KernelPlatform=exynos5, KernelARMPlatform=exynos5410 for example.

It is 16 bytes on 32-bit systems and 32 bytes on 64-bit systems

INTERNAL implies FORCE but in some versions of CMake if a config option
has been passed in via a -D option the INTERNAL set doesn't override the
value when it should.

See: https://gitlab.kitware.com/cmake/cmake/issues/19015
  INTERNAL does not imply FORCE for CACHE

All options that get unset are based on the selected platform and are
not allowed to be in the public config cache.

Instead of setting this option on each platform that supports aarch64,
we set it for all aarch64 platforms. It is expected that every valid
aarch64 platform has an FPU and will be correctly context switched by
the kernel.

These values are specified by the platform and not user configurable

At the stage where this is processed, Kernel32 hasn't been defined yet.

The UL_CONST macro was leading to a macro definition that didn't have
brackets around the addition and using the constant in negative
arithmetic operations was leading to incorrect results.

This change adds support for Hifive unleashed board. It also removes the
outdated hifive suport from the spike platform.

There is a different DTS file for 32bit spike platform.

The DTS compilation was arm platforms only. Moving it to the top level
config file, making it available to RISCV platforms. The generated files
are almost identical with minor differences. A new argument(--arch) is
added to the hardware_gen.py for the differences.

BeagleBone Blue is a BeagleBone variant aimed at robotics applications.
Device Tree generated from Linux 4.20.17

Overlay the incorrect memory size in the device tree, and enlarge the
kernel window appropriately.
BeagleBone Black has 512MiB memory.

Device Tree generated from Linux 4.20.17

There are other am335x boards which require different platform
configurations, such as the BeagleBone Blue.

The tk1 SMMU implementation does not need to dynamically allocate
memory as the PDs are not managed by user-level. Convert to static.

Add a device tree overlay such that all memory on the exynos4 fits in
the kernel window. It's unknown if the memory past 0x50000000 is valid,
when the elf-loader attempts to write to it it hangs.

This is workaround for part of binary verification, which currently
cannot handle some modes of array access.

If we place the user image at the end of memory, the user image can be
beyond the kernel window. Handle this in arch_init_freemem by comparing
to paddr's not pptrs.

This change allows us to know, from just the kernel and dtb, where user
level untyped objects start being allocated from.

- allocate rootserver objects from last available freemem region.
- move create_rootserver_objects call into init_freemem.

The user image could be on either side of mode_reserved_region. Fix this
by assuming there is 1 or 0 mode_reserved_regions, and checking if the
user image is either side.

This fails early if the build process failed to calculate a suitable
MAX_NUM_FREEMEM_REG.

Previously, the boot allocator would do dynamic calculations to
minimise fragmentation, then throw away the smallest regions.
With the new boot allocator, we can reasonably predict that
fragmentation will create at most one extra region, so this commit
adds one freemem slot for ARM.

Prior to this change, the boot process would dynamically allocate
memory for root server objects based on the order of initialisation.
Allocation was a best-fit algorithm.

This change preallocates all memory for root server objects to an
aligned untyped just after the user image. By allocating the objects in
order of size, allocation is greatly simplified and the ability to
reproduce the allocation offline based on the kernel and user image
sizes is increased.

Prior to this change, seL4_MappingFailedLookupLevel() would retrun '22'
after any failed EPT mapping operation. This change fixes this to return
the correct amount of unresolved bits in the address.

Cache `platform_yaml` so we can reference it from `elfloader-tool` CMake
logic.

- read PMUSERENR_ENABLE first before updating. On the cortex-a8
(specifically omap3) not doing this would result in the kernel aborting.
- do not read DBGDSCR_ext on cortex-a8, read DBGDSCR_int. This is only
implemented in armv7.1, not armv7, and also causes the kernel to abort.

These tools sometimes style differently across different versions.

With the increased faults on various configurations (hyp, mcs) we need
more bits to identify faults.

While masking and unmasking IRQs seems to work for some IRQ sources,
there are IRQ sources where masking an IRQ during a claim causes no
more IRQs to be raised after the IRQ is unmasked. This change
explicitly follows the claim->acknowledgement procedure that the
PLIC expects.

We add support for seL4_IRQControlGet and seL4_IRQControlGetTrigger. If
a platform doesn't support setting the trigger, then
seL4_IRQControlGetTrigger will return an error. If the platform doesn't
have a PLIC driver, then it won't have any IRQs that can be requested.

Also authored by: Siwei Zhuang <siwei.zhuang@data61.csiro.au>

Previously we only handled IRQs generated by the BBL running in machine
mode via changes to supervisor interrupt pending (SIP) bits. Now that we
need to support shared global interrupts through the PLIC we need to
modify the way interrupts are processed.

We additionally remove many DONT_TRANSLATE annotations on functions that
the CParser is able to parse.

Also authored by: Siwei Zhuang <siwei.zhuang@data61.csiro.au>

We assume the PLIC is currently the only global interrupt controller
that RISC-V platforms are going to use. Each platform may have a
different programmers model for interracting with the hardware
controller. We provide a common interface for PLIC drivers to implement
that the kernel will use to manage IRQs.

Also authored by: Siwei Zhuang <siwei.zhuang@data61.csiro.au>