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RISC-V GNU Toolchain
Commits
51c73700
Unverified
Commit
51c73700
authored
2 years ago
by
Christoph Müllner
Committed by
GitHub
2 years ago
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Merge pull request #1168 from riscv-collab/march-to-cpu-opt-unittest
Add unittest to march-to-cpu-opt
parents
b410695b
cb8f1a09
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scripts/march-to-cpu-opt
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51c73700
...
@@ -2,6 +2,7 @@
...
@@ -2,6 +2,7 @@
import
argparse
import
argparse
import
sys
import
sys
import
unittest
EXT_OPTS
=
{
EXT_OPTS
=
{
"
zba
"
:
"
zba=true
"
,
"
zba
"
:
"
zba=true
"
,
...
@@ -138,8 +139,22 @@ def conver_arch_to_qemu_cpu_opt(march):
...
@@ -138,8 +139,22 @@ def conver_arch_to_qemu_cpu_opt(march):
cpu_opt
.
append
(
"
d=false
"
)
cpu_opt
.
append
(
"
d=false
"
)
return
"
,
"
.
join
(
cpu_opt
)
return
"
,
"
.
join
(
cpu_opt
)
class
TestArchStringParse
(
unittest
.
TestCase
):
def
_test
(
self
,
arch
,
expected_arch_list
,
expected_vlen
=
0
):
exts
=
parse_march
(
arch
)
vlen
=
get_vlen
(
exts
)
self
.
assertEqual
(
expected_vlen
,
vlen
)
self
.
assertEqual
(
set
(
expected_arch_list
),
set
(
exts
.
keys
()))
def
test_rv64gc
(
self
):
self
.
_test
(
"
rv64gc
"
,
[
'
i
'
,
'
m
'
,
'
a
'
,
'
f
'
,
'
d
'
,
'
c
'
])
self
.
_test
(
"
rv32imc_zve32x
"
,
[
'
i
'
,
'
m
'
,
'
c
'
,
'
zve32x
'
],
expected_vlen
=
32
)
self
.
_test
(
"
rv32imc_zve32x_zvl128b
"
,
[
'
i
'
,
'
m
'
,
'
c
'
,
'
zve32x
'
,
'
zvl128b
'
],
expected_vlen
=
128
)
def
selftest
():
def
selftest
():
print
(
parse_march
(
"
rv64gc
"
)
)
unittest
.
main
(
argv
=
sys
.
argv
[
1
:]
)
def
main
(
argv
):
def
main
(
argv
):
opt
=
parse_opt
(
argv
)
opt
=
parse_opt
(
argv
)
...
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