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  • 2021.06.26
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  • 2021.04.23
    b715e4f0 · Bump riscv-binutils ·
  • 2021.04.07
  • 2021.04.03
  • 2021.03.26
  • 2021.03.17
  • 2021.03.06
    4e711512 · Remove travis-ci ·
  • 2021.01.26
  • rvv-0.8
  • before-fsf-gdb
  • v20180629   June 29th, 2018 Toolchain Release This release updates the toolchain to the latest upstream releases, including binutils-2.30, gcc-8.1, and newlib-3.0.0. We're still using the pre-upstream GDB and glibc ports.
  • v20171231   December 31st Toolchain Release It's been another month since the last toolchain release. The changes are fairly minor * binutils-gdb is still based on the 2.29 upstream release, with the following patches: * 248124ac2e57 RISC-V: Add missing privileged spec registers. * bee792f83a2a RISC-V: Add compressed instruction hints, and a few misc cleanups. * 7d895b6f4c12 Add missing RISC-V fsrmi and fsflagsi instructions. * 04d33e4a830b Objcopy interleave fails if section address not multiple of interleave. * 71a8fbb5aac3 Really fix riscv shared library __global_pointer$ problem. * 355497b4a723 Riscv shared libraries should not export __global_pointer$. * bfd4dc4363f4 Fix for texinfo 4.8. * caf839a4a41c Update and clean up RISC-V gas documentation. * df726395c987 Give Palmer co-credit for last patch. * 0362ab46dbe8 Fix riscv malloc error on small alignment after norvc. * 3adcc16f76e7 Merge pull request #126 from riscv/native-gdb * be4ba4074927 Make native gdb builds work. * 9b4d67248adb Merge pull request #122 from riscv/xml_registers * 58906a3ec0ad Remove redundant line. * 3a1de2c44f19 Don't need to track whether registers exist * c8f6c1bfeb6b Use gdbarch_ functions in case tdesc regs are used * 7d27e5408d3b Revert "Set target_desc in gdbarch_from_bfd()." * c6d3ad114dac Add helpful gdbarch comment * 0f5fee56333c Remove debug printfs. * de407c19e2c4 Set target_desc in gdbarch_from_bfd(). * 6b51d01bf018 Better handling of target description. * 12a42bd967c8 Copy helpful comment from arm-tdep. * b69b760d69ea Merge pull request #116 from kito-cheng/riscv-sim * cdc668285a26 Merge pull request #115 from timsifive/xml_registers * 52cca9ebe393 Incorporate review feedback. * c6a5890f348e Compress loads/stores with implicit 0 offset. * 8481854f09fa Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions, vis: fmv.x.w and fmv.w.x. * 396a0b13f8c9 Fix indention for TRACE_* * 80b28ad794ed Initialize end of brk to `_end` if possible * 9e22d669c3ce (sim) Return len even when modifying register ZERO. * 4229a5cce640 (sim) Add missing header * 1b223852172e (sim) Refine TARCE_INSN * 93ac92cd1209 Improve trace info for conditional branch * e62fa13662b0 Fix typo. * ae4c68f5dda0 Check brk if address is exceed DEFAULT_MEM_SIZE * 91bfc291c018 Change default size to 64M * 77a6f3bcbc7a Update cycleh and instreth at step_once * 66ea17cbfaf4 Implment csrrci, csrrsi and csrrwi * 5a79e80f4261 Support SYS_gettimeofday in gdb-sim. * 56be8b44c740 Add 'C' Compressed instructions for gdb simulator. * 5a60ae3657e2 (sim) Fix sbreak instruction. * ae36236bdd5e Fall back to use sim_syscall if we don't handle this syscall * 4fba6337cee8 Support SYS_brk in gdb-sim. * b5090c58bbbe Support SYS_link syscall in gdb-sim. * 5d87b1609050 First part of fix for riscv gas lns-common-1 failure. * b0ab42d9b0ea Add modified file I missed in last commit. * a8b34ad85ba6 Fix riscv ld testsuite failure for compressed1d. * 85ec95119d1d Fix riscv binutils xfail for debug_ranges test. * 6c510ac1e2de Fix typo in my email address. * 649a286a89e9 RISC-V: Fix riscv g++ testsuite EH failures. * 58e92db90d13 RISC-V: Add satp as an alias for sptbr * 6ac2ef3a3320 testsuite/ld-riscv-elf/ld-riscv-elf.exp: Fix typo for istarget. * 6e21f0139437 RISC-V: Add Jim Wilson as a maintainer, and clean up our entries * d42bfeceb523 Delete tconfig.h * 437ee82eeb54 Add 'D' double-precision instructions and 'F' single-precision instructions for gdb simulator * 08c5702eef14 Fix store or fetch correct fpr number. * c35211bb03c5 Initail stack pointer to 16byte aligned in both RV32 & RV64. * 2fdbbd7d12ab Fix atomic operation * fb4ba8f3bfc2 Use map to find registers instead of iterating. * d76b3d5a1d85 Remove unused field. * cd3e919468dd Only save/restore FP regs if they exist. * fee8ac5b2712 Add save/restore groups back. * e38628e067b3 Rebase cleanup. * 4f3bd83cd9e6 WIP on talking to servers that don't provide XML * c109cb7902a3 Checkpoint. XML registers pass spike32 tests. * 738db120fd4c Merge pull request #111 from riscv/register_names * 3ce8c2e6ae4a Merge pull request #112 from riscv/pseudo_registers * d0176cb1653b RISC-V: Fix riscv g++ testsuite EH failures. * d5feabfac32f RISC-V: Add satp as an alias for sptbr * 2f9782d95416 (WIP SIM): Fix jal and jalr * 13f665f5698d s0 is the preferred alias for x8. * d97ccfcb2112 We don't implement any pseudoregisters. * b11aca7dfa08 Use ABI names for registers. * f64577d1c916 RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0 * d51d92c4d06b RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2 * 3593f7f30f80 Fix my previous gas/ChangeLog entry * 164a62116dc9 RISC-V: Don't emit 2-byte NOPs if the C extension is disabled * 915b00e356e0 RISC-V: Relax RISCV_PCREL_* to RISCV_GPREL_* * fa753df2d560 RISC-V: Add R_RISCV_DELETE, which marks bytes for deletion * 9eb250cb914c RISC-V: Mark unsupported gas testcases * 0d96fbb3095f riscv: Cache the max alignment of output sections * 60cda8de81dc RISC-V: Avoid emitting invalid instructions in mixed RVC/no-RVC code * 296c682e9d92 RISC-V: Print an error when unable to align a section * 1bfb4ecbd84c RISC-V: Support PCREL_* relocations agaist weak undefined symbols * d3fae8db583d Improve handling of ADD and SUB relocations on the RISCV target. * 404de0666a6a RISC-V: Mark "c.nop" as an alias * dfbf9e44a0e1 Fix problems parsing RISCV architecture extenstions in the assembler. * 697d5b8ee280 (RISC-V GDB) Only save FPRs on harts that support F/D/Q * 495d737e62c0 (RISC-V GDB) GDB update * c950de297cd7 (RISC-V GDB) RISC-V GDB Port * GCC has not changed, it's still based on the 7.2.0 upstream release with the following changes * b731149757b9 ("RISC-V: Implement movmemsi") * 605bc7b5e06a ("RISC-V: Define MUSL_DYNAMIC_LINKER") * 2423096b0696 ("RISC-V: Emit "i" suffix for instructions with immediate operands") * 327d99b09bc0 ("RISC-V: If -m[no-]strict-align is not passed, assume its value from -mtune") * f34a83e82258 ("RISC-V: Set SLOW_BYTE_ACCESS=1") * 7dde69e2c5f7 ("RISC-V: Handle non-legitimate address in riscv_legitimize_move") * 1751fbe7b9e8 ("RISC-V: Use "@minus{}2 GB" instead of "-2 GB" in invoke.texi") * 6d1f1f891869 ("RISC-V: Document the medlow and medany code models") * d2d1f783b2c1 ("RISC-V: Correct and improve the "-mabi" documentation") * d13dd0242604 ("RISC-V: Add Sign/Zero extend patterns for PIC loads") * 341375637a7d ("RISC-V: Add -mstrict-align option") * f47f9c2b3b90 ("RISC-V: Unify indention in riscv.md") * 1bd23ca8c30f ("Update ChangeLog and version files for release")
    d66c792d · Bump binutils ·
  • v20171107   November 7th 2017 Toolchain Release It's been about two months since the last stable toolchain release, so we're a bit past due for a new one. Here's a summary of the changes in this release * binutils-gdb is still based on the 2.29 upstream release, with the following patches: * d0176cb1653b ("RISC-V: Fix riscv g++ testsuite EH failures.") * d5feabfac32f ("RISC-V: Add satp as an alias for sptbr") * 2f9782d95416 ("(WIP SIM): Fix jal and jalr") * f64577d1c916 ("RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0") * d51d92c4d06b ("RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2") * 3593f7f30f80 ("Fix my previous gas/ChangeLog entry") * 164a62116dc9 ("RISC-V: Don't emit 2-byte NOPs if the C extension is disabled") * 915b00e356e0 ("RISC-V: Relax RISCV_PCREL_* to RISCV_GPREL_*") * fa753df2d560 ("RISC-V: Add R_RISCV_DELETE, which marks bytes for deletion") * 9eb250cb914c ("RISC-V: Mark unsupported gas testcases") * 0d96fbb3095f ("riscv: Cache the max alignment of output sections") * 60cda8de81dc ("RISC-V: Avoid emitting invalid instructions in mixed RVC/no-RVC code") * 296c682e9d92 ("RISC-V: Print an error when unable to align a section") * 1bfb4ecbd84c ("RISC-V: Support PCREL_* relocations agaist weak undefined symbols") * d3fae8db583d ("Improve handling of ADD and SUB relocations on the RISCV target.") * 404de0666a6a ("RISC-V: Mark "c.nop" as an alias") * dfbf9e44a0e1 ("Fix problems parsing RISCV architecture extenstions in the assembler.") * 697d5b8ee280 ("(RISC-V GDB) Only save FPRs on harts that support F/D/Q") * 495d737e62c0 ("(RISC-V GDB) GDB update") * c950de297cd7 ("(RISC-V GDB) RISC-V GDB Port") * dd9a28c0966d ("Bump version to 2.29") * GCC is now based on the 7.2.0 upstream release, with the following patches * b731149757b9 ("RISC-V: Implement movmemsi") * 605bc7b5e06a ("RISC-V: Define MUSL_DYNAMIC_LINKER") * 2423096b0696 ("RISC-V: Emit "i" suffix for instructions with immediate operands") * 327d99b09bc0 ("RISC-V: If -m[no-]strict-align is not passed, assume its value from -mtune") * f34a83e82258 ("RISC-V: Set SLOW_BYTE_ACCESS=1") * 7dde69e2c5f7 ("RISC-V: Handle non-legitimate address in riscv_legitimize_move") * 1751fbe7b9e8 ("RISC-V: Use "@minus{}2 GB" instead of "-2 GB" in invoke.texi") * 6d1f1f891869 ("RISC-V: Document the medlow and medany code models") * d2d1f783b2c1 ("RISC-V: Correct and improve the "-mabi" documentation") * d13dd0242604 ("RISC-V: Add Sign/Zero extend patterns for PIC loads") * 341375637a7d ("RISC-V: Add -mstrict-align option") * f47f9c2b3b90 ("RISC-V: Unify indention in riscv.md") * 1bd23ca8c30f ("Update ChangeLog and version files for release")
    b4dae89f · Bump GCC ·
  • v20170612   June 12th 2017 Toolchain Release It's been a month since the last stable toolchain release, which seems like a good time for another one. Here's the changes since the last release: binutils * GP-relative disassembly hints are working again. * 32-bit BFDs can handle 64-bit objects. * c.li, c.andi, and c.addiw disassembly correctly. gcc * A new "-mstrict-align" option is availiable, which enforces strict alignment. Without this argument the compiler assumes unaligned operations are slow instead of assuming they're illegal. This is meant to be used in machine-mode code on platforms that don't support unaligned accesses. * Sub-XLEN PIC loads now extend correctly. * An internal compiler error related to sub-word moves has been fixed. glibc * The initial GP generation cannot be relaxed. newlib * We are using a version based on 2.5. riscv-gnu-toolchain * The prerequisite libraries are downloaded correctly again. * There is a "--with-guile" flag
    b7e00039 · The default ISA is GC ·