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  1. Jun 24, 2019
  2. Jun 20, 2019
    • Anna Lyons's avatar
      arm/tk1: make SMMU memory static · ce6d05e9
      Anna Lyons authored
      The tk1 SMMU implementation does not need to dynamically allocate
      memory as the PDs are not managed by user-level. Convert to static.
      ce6d05e9
    • Anna Lyons's avatar
      exynos4: clamp memory to fit in kernel window · c93c1c89
      Anna Lyons authored
      Add a device tree overlay such that all memory on the exynos4 fits in
      the kernel window. It's unknown if the memory past 0x50000000 is valid,
      when the elf-loader attempts to write to it it hangs.
      c93c1c89
    • Matthew Brecknell's avatar
      ARM boot: avoid variable + constant array access · 20ef7255
      Matthew Brecknell authored
      This is workaround for part of binary verification, which currently
      cannot handle some modes of array access.
      20ef7255
    • Anna Lyons's avatar
      boot: handle arm user image > kernel window · d4c106bf
      Anna Lyons authored
      If we place the user image at the end of memory, the user image can be
      beyond the kernel window. Handle this in arch_init_freemem by comparing
      to paddr's not pptrs.
      d4c106bf
    • Anna Lyons's avatar
      boot: allocate rootserver objects last · cb7cbd84
      Anna Lyons authored
      This change allows us to know, from just the kernel and dtb, where user
      level untyped objects start being allocated from.
      
      - allocate rootserver objects from last available freemem region.
      - move create_rootserver_objects call into init_freemem.
      cb7cbd84
    • Anna Lyons's avatar
      arm: handle user image being at end of memory · 6db7bf9b
      Anna Lyons authored
      The user image could be on either side of mode_reserved_region. Fix this
      by assuming there is 1 or 0 mode_reserved_regions, and checking if the
      user image is either side.
      6db7bf9b
    • Japheth Lim's avatar
      ARM boot: abort if out of freemem slots · 4a3685df
      Japheth Lim authored
      This fails early if the build process failed to calculate a suitable
      MAX_NUM_FREEMEM_REG.
      4a3685df
    • Japheth Lim's avatar
      ARM boot: MAX_NUM_FREEMEM_REG++ for new allocator · e42700a4
      Japheth Lim authored
      Previously, the boot allocator would do dynamic calculations to
      minimise fragmentation, then throw away the smallest regions.
      With the new boot allocator, we can reasonably predict that
      fragmentation will create at most one extra region, so this commit
      adds one freemem slot for ARM.
      e42700a4
    • Anna Lyons's avatar
      trivial: VspaceBits -> VSpaceBits on riscv32 · 5f8e3615
      Anna Lyons authored
      5f8e3615
    • Anna Lyons's avatar
      boot: refactor allocation of rootserver objects · 8586b7f2
      Anna Lyons authored
      Prior to this change, the boot process would dynamically allocate
      memory for root server objects based on the order of initialisation.
      Allocation was a best-fit algorithm.
      
      This change preallocates all memory for root server objects to an
      aligned untyped just after the user image. By allocating the objects in
      order of size, allocation is greatly simplified and the ability to
      reproduce the allocation offline based on the kernel and user image
      sizes is increased.
      8586b7f2
    • Anna Lyons's avatar
      x86/ept: return correct MappingFailedLookupLevel · 90c49746
      Anna Lyons authored
      Prior to this change, seL4_MappingFailedLookupLevel() would retrun '22'
      after any failed EPT mapping operation. This change fixes this to return
      the correct amount of unresolved bits in the address.
      90c49746
  3. Jun 19, 2019
    • G. Branden Robinson's avatar
      src/arch/arm/config.cmake: cache platform_yaml · 2e79f2ed
      G. Branden Robinson authored
      Cache `platform_yaml` so we can reference it from `elfloader-tool` CMake
      logic.
      2e79f2ed
    • Anna Lyons's avatar
      cortex-a8: fix check_export_pmu · 81316c5b
      Anna Lyons authored
      - read PMUSERENR_ENABLE first before updating. On the cortex-a8
      (specifically omap3) not doing this would result in the kernel aborting.
      - do not read DBGDSCR_ext on cortex-a8, read DBGDSCR_int. This is only
      implemented in armv7.1, not armv7, and also causes the kernel to abort.
      81316c5b
  4. Jun 18, 2019
    • Kent McLeod's avatar
      python,sel4-deps: Pin versions for style tools · 664ac228
      Kent McLeod authored
      These tools sometimes style differently across different versions.
      664ac228
    • Anna Lyons's avatar
      Update seL4_FaultType to 4 · f3d0eb20
      Anna Lyons authored
      With the increased faults on various configurations (hyp, mcs) we need
      more bits to identify faults.
      f3d0eb20
    • Kent McLeod's avatar
      RISC-V,PLIC: Cannot mask and unmask claimed IRQ · 1f84a048
      Kent McLeod authored
      While masking and unmasking IRQs seems to work for some IRQ sources,
      there are IRQ sources where masking an IRQ during a claim causes no
      more IRQs to be raised after the IRQ is unmasked. This change
      explicitly follows the claim->acknowledgement procedure that the
      PLIC expects.
      1f84a048
    • Kent McLeod's avatar
      Add RISC-V IRQ invocations · 4ce8f0a9
      Kent McLeod authored
      We add support for seL4_IRQControlGet and seL4_IRQControlGetTrigger. If
      a platform doesn't support setting the trigger, then
      seL4_IRQControlGetTrigger will return an error. If the platform doesn't
      have a PLIC driver, then it won't have any IRQs that can be requested.
      
      Also authored by: Siwei Zhuang <siwei.zhuang@data61.csiro.au>
      4ce8f0a9
    • Kent McLeod's avatar
      RISC-V: Refactor IRQ handling to use PLIC · 9a552d84
      Kent McLeod authored
      Previously we only handled IRQs generated by the BBL running in machine
      mode via changes to supervisor interrupt pending (SIP) bits. Now that we
      need to support shared global interrupts through the PLIC we need to
      modify the way interrupts are processed.
      
      We additionally remove many DONT_TRANSLATE annotations on functions that
      the CParser is able to parse.
      
      Also authored by: Siwei Zhuang <siwei.zhuang@data61.csiro.au>
      9a552d84
    • Kent McLeod's avatar
      RISC-V: Add PLIC interface and HiFive driver · c73d5178
      Kent McLeod authored
      We assume the PLIC is currently the only global interrupt controller
      that RISC-V platforms are going to use. Each platform may have a
      different programmers model for interracting with the hardware
      controller. We provide a common interface for PLIC drivers to implement
      that the kernel will use to manage IRQs.
      
      Also authored by: Siwei Zhuang <siwei.zhuang@data61.csiro.au>
      c73d5178
    • Siwei Zhuang's avatar
      RISC-V: Add kernel device functionalty · 4b240066
      Siwei Zhuang authored
      - Create device untypeds for platform devices that can be passed to user
      space.
      - Create kernel device mapping for devices required by the kernel.
      Note that the current kernel device mapping is simply a 1GiB of page
      physical memory as that contains all devices for all RISC-V platforms
      that are currently supported.
      4b240066
  5. Jun 17, 2019
  6. Jun 14, 2019
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