Inline resetTimer for all platforms

- for arm generic timer platforms, we remove resetTimer ->
resetGenericTimer indirection and simply include generic_timer.h
- this reduces boiler plate for platforms that share timer drivers, as
  they simply include the one header
- there is far more timer code in the RT kernel, which motivates this
change

include/arch/arm/arch/machine/generic_timer.h

@@ -15,13 +15,12 @@
 
 #include <config.h>
 #include <arch/machine/timer.h>
-#include <plat/machine/timer.h>
 #include <mode/machine.h>
 
 /* ARM generic timer implementation */
 
 static inline void
-resetGenericTimer(void)
+resetTimer(void)
 {
     SYSTEM_WRITE_WORD(CNT_TVAL, TIMER_RELOAD);
     SYSTEM_WRITE_WORD(CNT_CTL, BIT(0));

include/arch/arm/arch/machine/priv_timer.h

@@ -14,5 +14,20 @@
 #define __ARCH_MACHINE_PRIV_TIMER_H_
 
 #define TIMER_CLOCK_HZ 400000000ULL
+#define TMR_INTS_EVENT       BIT(0)
+
+/* 32 bit down counter */
+struct timer {
+    uint32_t load;
+    uint32_t count;
+    uint32_t ctrl;
+    uint32_t ints;
+};
+typedef volatile struct timer timer_t;
+extern timer_t *priv_timer;
+
+static inline void resetTimer(void) {
+    priv_timer->ints = TMR_INTS_EVENT;
+}
 
 #endif /* __ARCH_MACHINE_PRIV_TIMER_H_ */

include/machine/timer.h

@@ -10,6 +10,6 @@
 #ifndef __TIMER_H
 #define __TIMER_H
 
-void resetTimer(void);
+static inline void resetTimer(void);
 
 #endif

include/plat/allwinnerA20/plat/machine/timer.h

@@ -14,5 +14,22 @@
 #define __PLAT_MACHINE_TIMER_H
 
 #define TIMER_CLOCK_HZ 24000000ULL
+#define TMR0_IRQ_PEND_FLAG          BIT(0)
+
+struct timer {
+    uint32_t tmr_irq_en_reg;        /* Timer IRQ Enable Register 0x00 */
+    uint32_t tmr_irq_sta_reg;       /* Timer Status Register  0x04 */
+    uint32_t tmr_reserved01[2];
+    uint32_t tmr0_ctrl_reg;         /* Timer 0 Control Register  0x10 */
+    uint32_t tmr0_intv_value_reg;   /* Timer 0 Interval Value Register 0x14 */
+    uint32_t tmr0_cur_value_reg;    /* Timer 0 Current Value Register  0x18 */
+};
+typedef volatile struct timer timer_t;
+extern timer_t *timer;
+
+static inline void resetTimer(void)
+{
+	timer->tmr_irq_sta_reg = TMR0_IRQ_PEND_FLAG;
+}
 
 #endif /* !__PLAT_MACHINE_TIMER_H */

include/plat/am335x/plat/machine/timer.h

@@ -13,6 +13,40 @@
 #ifndef __PLAT_MACHINE_TIMER_H
 #define __PLAT_MACHINE_TIMER_H
 
+#include <plat/machine/interrupt.h>
+
 #define TIMER_CLOCK_HZ 32768llu // 32KHz
 
+#define TISR_OVF_FLAG (BIT(0) | BIT(1) | BIT(2))
+
+struct timer {
+    uint32_t tidr; // 00h TIDR Identification Register
+    uint32_t padding1[3];
+    uint32_t cfg; // 10h TIOCP_CFG Timer OCP Configuration Register
+    uint32_t padding2[3];
+    uint32_t tieoi; // 20h IRQ_EOI Timer IRQ End-Of-Interrupt Register
+    uint32_t tisrr; // 24h IRQSTATUS_RAW Timer IRQSTATUS Raw Register
+    uint32_t tisr; // 28h IRQSTATUS Timer IRQSTATUS Register
+    uint32_t tier; // 2Ch IRQSTATUS_SET Timer IRQENABLE Set Register
+    uint32_t ticr; // 30h IRQSTATUS_CLR Timer IRQENABLE Clear Register
+    uint32_t twer; // 34h IRQWAKEEN Timer IRQ Wakeup Enable Register
+    uint32_t tclr; // 38h TCLR Timer Control Register
+    uint32_t tcrr; // 3Ch TCRR Timer Counter Register
+    uint32_t tldr; // 40h TLDR Timer Load Register
+    uint32_t ttgr; // 44h TTGR Timer Trigger Register
+    uint32_t twps; // 48h TWPS Timer Write Posted Status Register
+    uint32_t tmar; // 4Ch TMAR Timer Match Register
+    uint32_t tcar1; // 50h TCAR1 Timer Capture Register
+    uint32_t tsicr; // 54h TSICR Timer Synchronous Interface Control Register
+    uint32_t tcar2; // 58h TCAR2 Timer Capture Register
+};
+typedef volatile struct timer timer_t;
+extern timer_t *timer;
+
+static inline void resetTimer(void)
+{
+    timer->tisr = TISR_OVF_FLAG;
+    ackInterrupt(DMTIMER0_IRQ);
+}
+
 #endif /* !__PLAT_MACHINE_TIMER_H */

include/plat/apq8064/plat/machine/timer.h

@@ -15,4 +15,8 @@
 
 #define TIMER_CLOCK_HZ 7000000llu
 
+static inline void resetTimer(void) {
+    /* Nothing to do */
+}
+
 #endif /* !__PLAT_MACHINE_TIMER_H */

include/plat/bcm2837/plat/machine/timer.h

@@ -15,4 +15,6 @@
 
 #define TIMER_CLOCK_HZ 19200000llu
 
+#include <arch/machine/generic_timer.h>
+
 #endif /* !__PLAT_MACHINE_TIMER_H */

include/plat/exynos4/plat/machine/timer.h

@@ -13,6 +13,12 @@
 #ifndef __PLAT_MACHINE_TIMER_H
 #define __PLAT_MACHINE_TIMER_H
 
+#include <plat/machine/mct.h>
+
 #define TIMER_CLOCK_HZ 24000000llu
 
+static inline void resetTimer(void) {
+    mct_reset();
+}
+
 #endif /* !__PLAT_MACHINE_TIMER_H */

include/plat/exynos5/plat/machine/timer.h

@@ -15,4 +15,6 @@
 
 #define TIMER_CLOCK_HZ 24000000llu
 
+#include <arch/machine/generic_timer.h>
+
 #endif /* !__PLAT_MACHINE_TIMER_H */

include/plat/hikey/plat/machine/timer.h

@@ -15,4 +15,6 @@
 
 #define TIMER_CLOCK_HZ 1200000llu
 
+#include <arch/machine/generic_timer.h>
+
 #endif /* !__PLAT_MACHINE_TIMER_H */

include/plat/imx31/plat/machine/timer.h

@@ -15,4 +15,21 @@
 
 #define TIMER_CLOCK_HZ 32768llu
 
+/* Memory map for EPIT (Enhanced Periodic Interrupt Timer). */
+struct timer {
+    uint32_t epitcr;
+    uint32_t epitsr;
+    uint32_t epitlr;
+    uint32_t epitcmpr;
+    uint32_t epitcnt;
+};
+typedef volatile struct timer timer_t;
+extern timer_t *epit1;
+
+static inline void resetTimer(void)
+{
+    epit1->epitsr = 1;
+    /* Timer resets automatically */
+}
+
 #endif /* !__PLAT_MACHINE_TIMER_H */

include/plat/imx7/plat/machine/timer.h

@@ -15,4 +15,6 @@
 
 #define TIMER_CLOCK_HZ 8000000llu
 
+#include <arch/machine/generic_timer.h>
+
 #endif /* !__PLAT_MACHINE_TIMER_H */

include/plat/omap3/plat/machine/timer.h

@@ -13,6 +13,41 @@
 #ifndef __PLAT_MACHINE_TIMER_H
 #define __PLAT_MACHINE_TIMER_H
 
+#include <plat/machine/interrupt.h>
+
 #define TIMER_CLOCK_HZ 13000000llu
+#define TISR_OVF_FLAG       BIT(1)
+
+struct timer {
+    uint32_t tidr;   /* GPTIMER_TIDR 0x00 */
+    uint32_t padding1[3];
+    uint32_t cfg;    /* GPTIMER_CFG 0x10 */
+    uint32_t tistat; /* GPTIMER_TISTAT 0x14 */
+    uint32_t tisr;   /* GPTIMER_TISR 0x18 */
+    uint32_t tier;   /* GPTIMER_TIER 0x1C */
+    uint32_t twer;   /* GPTIMER_TWER 0x20 */
+    uint32_t tclr;   /* GPTIMER_TCLR 0x24 */
+    uint32_t tcrr;   /* GPTIMER_TCRR 0x28 */
+    uint32_t tldr;   /* GPTIMER_TLDR 0x2C */
+    uint32_t ttgr;   /* GPTIMER_TTGR 0x30 */
+    uint32_t twps;   /* GPTIMER_TWPS 0x34 */
+    uint32_t tmar;   /* GPTIMER_TMAR 0x38 */
+    uint32_t tcar1;  /* GPTIMER_TCAR1 0x3C */
+    uint32_t tsicr;  /* GPTIMER_TSICR 0x40 */
+    uint32_t tcar2;  /* GPTIMER_TCAR2 0x44 */
+    uint32_t tpir;   /* GPTIMER_TPIR 0x48 */
+    uint32_t tnir;   /* GPTIMER_TNIR 0x4C */
+    uint32_t tcvr;   /* GPTIMER_TCVR 0x50 */
+    uint32_t tocr;   /* GPTIMER_TOCR 0x54 */
+    uint32_t towr;   /* GPTIMER_TOWR 0x58 */
+};
+typedef volatile struct timer timer_t;
+extern timer_t *timer;
+
+static inline void resetTimer(void)
+{
+    timer->tisr = TISR_OVF_FLAG;
+    ackInterrupt(GPT9_IRQ);
+}
 
 #endif /* !__PLAT_MACHINE_TIMER_H */

include/plat/pc99/plat/machine/timer.h

+/*
+ * Copyright 2017, Data61
+ * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
+ * ABN 41 687 119 230.
+ *
+ * This software may be distributed and modified according to the terms of
+ * the GNU General Public License version 2. Note that NO WARRANTY is provided.
+ * See "LICENSE_GPLv2.txt" for details.
+ *
+ * @TAG(DATA61_GPL)
+ */
+
+#ifndef __PLAT_MACHINE_TIMER_H
+#define __PLAT_MACHINE_TIMER_H
+
+static inline void resetTimer()
+{
+    /* nothing to do */
+}
+
+#endif /* !__PLAT_MACHINE_TIMER_H */

include/plat/tk1/plat/machine/timer.h

@@ -15,4 +15,6 @@
 
 #define TIMER_CLOCK_HZ 12000000llu
 
+#include <arch/machine/generic_timer.h>
+
 #endif /* !__PLAT_MACHINE_TIMER_H */

include/plat/tx1/plat/machine/timer.h

@@ -15,4 +15,6 @@
 
 #define TIMER_CLOCK_HZ 19200000llu
 
+#include <arch/machine/generic_timer.h>
+
 #endif /* !__PLAT_MACHINE_TIMER_H */

include/plat/zynqmp/plat/machine/timer.h

@@ -15,4 +15,6 @@
 
 #define TIMER_CLOCK_HZ 100000000llu
 
+#include <arch/machine/generic_timer.h>
+
 #endif /* !__PLAT_MACHINE_TIMER_H */

src/arch/arm/machine/generic_timer.c

@@ -10,6 +10,7 @@
  * @TAG(DATA61_GPL)
  */
 
+#include <plat/machine/timer.h>
 #include <arch/machine/generic_timer.h>
 
 BOOT_CODE void initGenericTimer(void)
@@ -24,5 +25,5 @@ BOOT_CODE void initGenericTimer(void)
         }
     }
 
-    resetGenericTimer();
+    resetTimer();
 }

src/arch/arm/machine/priv_timer.c

@@ -13,21 +13,12 @@
 #include <arch/machine/timer.h>
 #include <arch/machine/priv_timer.h>
 
-/* 32 bit down counter */
-struct timer {
-    uint32_t load;
-    uint32_t count;
-    uint32_t ctrl;
-    uint32_t ints;
-};
-typedef volatile struct timer timer_t;
 timer_t *priv_timer = (timer_t *) ARM_MP_PRIV_TIMER_PPTR;
 
 #define TMR_CTRL_ENABLE      BIT(0)
 #define TMR_CTRL_AUTORELOAD  BIT(1)
 #define TMR_CTRL_IRQEN       BIT(2)
 #define TMR_CTRL_PRESCALE    8
-#define TMR_INTS_EVENT       BIT(0)
 
 #define TIMER_INTERVAL_MS    (CONFIG_TIMER_TICK_MS)
 #define TIMER_COUNT_BITS 32
@@ -50,10 +41,3 @@ initTimer(void)
     /* Enable */
     priv_timer->ctrl |= TMR_CTRL_ENABLE;
 }
-
-void
-resetTimer(void)
-{
-    priv_timer->ints = TMR_INTS_EVENT;
-}
-

src/object/interrupt.c

@@ -22,6 +22,7 @@
 #include <kernel/thread.h>
 #include <model/statedata.h>
 #include <machine/timer.h>
+#include <plat/machine/timer.h>
 #include <smp/ipi.h>
 
 exception_t