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Commit bdc56112 authored by Anna Lyons's avatar Anna Lyons Committed by Kent Mcleod
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arm: tickless generic timer implementation

Update the generic timer to implement the MCS kernels tickless timer
driver API and update all platforms that use the arm generic timers:

    - bcm2837
    - exynos5
    - hikey
    - imx7
    - odroidc2
    - tk1
    - tx1
    - tx2
    - zynq7000

Also move the generic timer constants to machine.h to avoid a circular
dependency.
parent a7fb6b56
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Showing with 84 additions and 27 deletions
......@@ -64,6 +64,20 @@
#define ID_PFR1 " p15, 0, %0, c0, c1, 1" /* 32-bit RO CPU feature register */
#define CPACR " p15, 0, %0, c1, c0, 2" /* 32-bit Architectural Feature Access Control Register */
/* Use Hypervisor Physical timer */
#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
#define CNT_TVAL CNTHP_TVAL
#define CNT_CT CNTPCT
#define CNT_CTL CNTHP_CTL
#define CNT_CVAL CNTHP_CVAL
#else
/* Use virtual timer */
#define CNT_TVAL CNTV_TVAL
#define CNT_CT CNTVCT
#define CNT_CTL CNTV_CTL
#define CNT_CVAL CNTV_CVAL
#endif
#ifdef ENABLE_SMP_SUPPORT
/* Use the first two SGI (Software Generated Interrupt) IDs
* for seL4 IPI implementation. SGIs are per-core banked.
......
......@@ -15,20 +15,6 @@
#include <config.h>
#include <stdint.h>
#include <plat/machine/hardware.h>
#include <mode/machine.h>
/* Use Hypervisor Physical timer */
#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
#define CNT_TVAL CNTHP_TVAL
#define CNT_CTL CNTHP_CTL
#define CNT_CVAL CNTHP_CVAL
#else
/* Use virtual timer */
#define CNT_TVAL CNTV_TVAL
#define CNT_CTL CNTV_CTL
#define CNT_CVAL CNTV_CVAL
#endif
#ifdef CONFIG_KERNEL_MCS
#include <util.h>
......
......@@ -26,6 +26,18 @@
#include <mode/machine_pl2.h>
#include <mode/hardware.h>
#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
#define CNT_TVAL "cnthp_tval_el2"
#define CNT_CVAL "cnthp_cval_el2"
#define CNT_CTL "cnthp_ctl_el2"
#else
#define CNT_TVAL "cntv_tval_el0"
#define CNT_CVAL "cntv_cval_el0"
#define CNT_CTL "cntv_ctl_el0"
#endif
#define CNTFRQ "cntfrq_el0"
#define CNT_CT "cntvct_el0"
#ifdef ENABLE_SMP_SUPPORT
/* Use the first two SGI (Software Generated Interrupt) IDs
* for seL4 IPI implementation. SGIs are per-core banked.
......
......@@ -14,18 +14,6 @@
#define __ARCH_MODE_MACHINE_TIMER_H_
#include <config.h>
#include <plat/machine/hardware.h>
#include <mode/machine.h>
#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
#define CNT_TVAL "cnthp_tval_el2"
#define CNT_CTL "cnthp_ctl_el2"
#else
#define CNT_TVAL "cntv_tval_el0"
#define CNT_CTL "cntv_ctl_el0"
#endif
#define CNTFRQ "cntfrq_el0"
#ifdef CONFIG_KERNEL_MCS
#include <stdint.h>
#include <util.h>
......
......@@ -14,16 +14,40 @@
#define __DRIVERS_TIMER_ARM_GENERIC_H_
#include <config.h>
#include <arch/machine/timer.h>
#include <mode/machine.h>
/* ARM generic timer implementation */
#ifdef CONFIG_KERNEL_MCS
#include <model/statedata.h>
#include <api/types.h>
/** DONT_TRANSLATE **/
static inline ticks_t getCurrentTime(void)
{
ticks_t time;
SYSTEM_READ_64(CNT_CT, time);
return time;
}
/** DONT_TRANSLATE **/
static inline void setDeadline(ticks_t deadline)
{
assert(deadline >= NODE_STATE(ksCurTime));
SYSTEM_WRITE_64(CNT_CVAL, deadline);
}
static inline void ackDeadlineIRQ(void)
{
ticks_t deadline = UINT64_MAX;
setDeadline(deadline);
}
#else /* CONFIG_KERNEL_MCS */
#include <arch/machine/timer.h>
static inline void resetTimer(void)
{
SYSTEM_WRITE_WORD(CNT_TVAL, TIMER_RELOAD);
SYSTEM_WRITE_WORD(CNT_CTL, BIT(0));
}
#endif /* !CONFIG_KERNEL_MCS */
BOOT_CODE void initGenericTimer(void);
......
......@@ -25,7 +25,13 @@ BOOT_CODE void initGenericTimer(void)
}
}
#ifdef CONFIG_KERNEL_MCS
/* this sets the irq to UINT64_MAX */
ackDeadlineIRQ();
SYSTEM_WRITE_WORD(CNT_CTL, BIT(0));
#else /* CONFIG_KERNEL_MCS */
resetTimer();
#endif /* !CONFIG_KERNEL_MCS */
}
/*
......
......@@ -38,6 +38,9 @@ if(KernelPlatformRpi3)
MAX_IRQ 127
TIMER drivers/timer/arm_generic.h
INTERRUPT_CONTROLLER drivers/irq/bcm2836-armctrl-ic.h
KERNEL_WCET 10u
CLK_MAGIC 458129845llu
CLK_SHIFT 43u
)
endif()
......
......@@ -75,6 +75,9 @@ if(KernelPlatExynos5)
NUM_PPI 32
TIMER drivers/timer/arm_generic.h
INTERRUPT_CONTROLLER arch/machine/gic_v2.h
CLK_MAGIC 2863311531llu
CLK_SHIFT 36u
KERNEL_WCET 10u
)
endif()
......
......@@ -37,6 +37,9 @@ if(KernelPlatformHikey)
MAX_IRQ 159
TIMER drivers/timer/arm_generic.h
INTERRUPT_CONTROLLER arch/machine/gic_v2.h
CLK_MAGIC 458129845llu
CLK_SHIFT 39u
KERNEL_WCET 10u
)
endif()
......
......@@ -28,6 +28,9 @@ if(KernelPlatImx7)
NUM_PPI 32
TIMER drivers/timer/arm_generic.h
INTERRUPT_CONTROLLER arch/machine/gic_v2.h
CLK_MAGIC 1llu
CLK_SHIFT 8u
KERNEL_WCET 10u
)
else()
config_set(KernelPlatImx7 PLAT_IMX7 OFF)
......
......@@ -28,6 +28,9 @@ if(KernelPlatformOdroidc2)
NUM_PPI 32
TIMER drivers/timer/arm_generic.h
INTERRUPT_CONTROLLER arch/machine/gic_v2.h
CLK_MAGIC 375299969u
CLK_SHIFT 53u
KERNEL_WCET 10u
)
endif()
......
......@@ -37,6 +37,9 @@ if(KernelPlatformTK1)
INTERRUPT_CONTROLLER arch/machine/gic_v2.h
NUM_PPI 32
TIMER drivers/timer/arm_generic.h SMMU plat/machine/smmu.h
CLK_MAGIC 2863311531llu
CLK_SHIFT 35u
KERNEL_WCET 10u
)
endif()
......
......@@ -28,6 +28,9 @@ if(KernelPlatformTx1)
INTERRUPT_CONTROLLER arch/machine/gic_v2.h
NUM_PPI 32
TIMER drivers/timer/arm_generic.h
CLK_MAGIC 458129845llu
CLK_SHIFT 43u
KERNEL_WCET 10u
)
endif()
......
......@@ -30,6 +30,9 @@ if(KernelPlatformTx2)
INTERRUPT_CONTROLLER arch/machine/gic_v2.h
NUM_PPI 32
TIMER drivers/timer/arm_generic.h
CLK_SHIFT 57u
CLK_MAGIC 4611686019u
KERNEL_WCET 10u
)
endif()
......
......@@ -49,6 +49,9 @@ if(KernelPlatformZynqmp)
NUM_PPI 32
TIMER drivers/timer/arm_generic.h
INTERRUPT_CONTROLLER arch/machine/gic_v2.h
CLK_MAGIC 1374389535llu
CLK_SHIFT 37u
KERNEL_WCET 10u
)
endif()
......
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