Skip to content
Snippets Groups Projects
Commit 969c8b93 authored by Kent McLeod's avatar Kent McLeod
Browse files

gic_500: Use GIC v3 register definitions 

This is in preparation for providing this driver as a generic GIC v3
driver.
parent c33d5e5a
No related branches found
No related tags found
No related merge requests found
Hide whitespace changes
Inline Side-by-side
include/arch/arm/arch/machine/gic_500.h
+ 39
− 61
View file @ 969c8b93
......@@ -63,11 +63,6 @@ enum irqNumbers {
#define GICD_CTLR_ENABLE_G0 BIT(0)
#define GICD_IROUTER_SPI_MODE_ANY BIT(31)
/* Common between GICD_PIDR2 and GICR_PIDR2 */
#define GIC_PIDR2_ARCH_MASK (0xf0)
#define GIC_PIDR2_ARCH_GICv3 (0x30)
#define GIC_PIDR2_ARCH_GICv4 (0x40)
#define GICD_TYPE_LINESNR 0x01f
#define GICC_SRE_EL1_SRE BIT(0)
......@@ -95,7 +90,9 @@ struct gic_dist_map {
uint32_t ctlr; /* 0x0000 */
uint32_t typer; /* 0x0004 */
uint32_t iidr; /* 0x0008 */
uint32_t res1[13]; /* [0x000C, 0x0040) */
uint32_t res0; /* 0x000C */
uint32_t statusr; /* 0x0010 */
uint32_t res1[11]; /* [0x0014, 0x0040) */
uint32_t setspi_nsr; /* 0x0040 */
uint32_t res2; /* 0x0044 */
uint32_t clrspi_nsr; /* 0x0048 */
......@@ -106,63 +103,50 @@ struct gic_dist_map {
uint32_t res5[9]; /* [0x005C, 0x0080) */
uint32_t igrouprn[32]; /* [0x0080, 0x0100) */
uint32_t enable_set[32]; /* [0x100, 0x180) */
uint32_t enable_clr[32]; /* [0x180, 0x200) */
uint32_t pending_set[32]; /* [0x200, 0x280) */
uint32_t pending_clr[32]; /* [0x280, 0x300) */
uint32_t active_set[32]; /* [0x300, 0x380) */
uint32_t active_clr[32]; /* [0x380, 0x400) */
uint32_t isenablern[32]; /* [0x100, 0x180) */
uint32_t icenablern[32]; /* [0x180, 0x200) */
uint32_t ispendrn[32]; /* [0x200, 0x280) */
uint32_t icpendrn[32]; /* [0x280, 0x300) */
uint32_t isactivern[32]; /* [0x300, 0x380) */
uint32_t icactivern[32]; /* [0x380, 0x400) */
uint32_t priority[255]; /* [0x400, 0x7FC) */
uint32_t ipriorityrn[255]; /* [0x400, 0x7FC) */
uint32_t res6; /* 0x7FC */
uint32_t targets[255]; /* [0x800, 0xBFC) */
uint32_t res7; /* 0xBFC */
uint32_t itargetsrn[254]; /* [0x800, 0xBF8) */
uint32_t res7[2]; /* 0xBF8 */
uint32_t config[64]; /* [0xC00, 0xD00) */
uint32_t group_mod[64]; /* [0xD00, 0xE00) */
uint32_t nsacr[64]; /* [0xE00, 0xF00) */
uint32_t icfgrn[64]; /* [0xC00, 0xD00) */
uint32_t igrpmodrn[64]; /* [0xD00, 0xE00) */
uint32_t nsacrn[64]; /* [0xE00, 0xF00) */
uint32_t sgir; /* 0xF00 */
uint32_t res8[3]; /* [0xF00, 0xF10) */
uint32_t sgi_pending_clr[4]; /* [0xF10, 0xF20) */
uint32_t sgi_pending_set[4]; /* [0xF20, 0xF30) */
uint32_t res8[3]; /* [0xF04, 0xF10) */
uint32_t cpendsgirn[4]; /* [0xF10, 0xF20) */
uint32_t spendsgirn[4]; /* [0xF20, 0xF30) */
uint32_t res9[5235]; /* [0x0F30, 0x6100) */
uint64_t irouter[960]; /* [0x6100, 0x7F00) */
uint64_t res10[2080]; /* [0x7F00, 0xC000) */
uint32_t estatusr; /* 0xC000 */
uint32_t errtestr; /* 0xC004 */
uint32_t res11[31]; /* [0xC008, 0xC084) */
uint32_t spisr[30]; /* [0xC084, 0xC0FC) */
uint32_t res12[4021]; /* [0xC0FC, 0xFFD0) */
uint32_t pidrn[8]; /* [0xFFD0, 0xFFF0) */
uint32_t cidrn[4]; /* [0xFFD0, 0xFFFC] */
uint64_t iroutern[960]; /* [0x6100, 0x7F00) */
};
/* Memory map for GIC Redistributor Registers for control and physical LPI's */
struct gic_rdist_map { /* Starting */
uint32_t ctlr; /* 0x0000 */
uint32_t iidr; /* 0x0004 */
uint64_t typer; /* 0x008 */
uint32_t res0; /* 0x0010 */ /*Would be the status register, but that is not implemented in the GIC-500*/
uint64_t typer; /* 0x0008 */
uint32_t statusr; /* 0x0010 */
uint32_t waker; /* 0x0014 */
uint32_t res1[21]; /* 0x0018 */
uint32_t res0[10]; /* 0x0018 */
uint64_t setlpir; /* 0x0040 */
uint64_t clrlpir; /* 0x0048 */
uint32_t res1[8]; /* 0x0050 */
uint64_t propbaser; /* 0x0070 */
uint64_t pendbaser; /* 0x0078 */
uint32_t res2[16340]; /* 0x0080 */
uint32_t pidr4; /* 0xFFD0 */
uint32_t pidr5; /* 0xFFD4 */
uint32_t pidr6; /* 0xFFD8 */
uint32_t pidr7; /* 0xFFDC */
uint32_t pidr0; /* 0xFFE0 */
uint32_t pidr1; /* 0xFFE4 */
uint32_t pidr2; /* 0xFFE8 */
uint32_t pidr3; /* 0xFFEC */
uint32_t cidr0; /* 0xFFF0 */
uint32_t cidr1; /* 0xFFF4 */
uint32_t cidr2; /* 0xFFF8 */
uint32_t cidr3; /* 0xFFFC */
uint32_t res2[8]; /* 0x0080 */
uint64_t invlpir; /* 0x00a0 */
uint32_t res3[2]; /* 0x00a8 */
uint64_t invallr; /* 0x00b0 */
uint32_t res4[2]; /* 0x00b8 */
uint32_t syncr; /* 0x00c0 */
};
/* Memory map for the GIC Redistributor Registers for the SGI and PPI's */
......@@ -184,18 +168,12 @@ struct gic_rdist_sgi_ppi_map { /* Starting */
uint32_t res7[31]; /* 0x0384 */
uint32_t ipriorityrn[8]; /* 0x0400 */
uint32_t res8[504]; /* 0x0420 */
uint32_t icfgrn_ro; /* 0x0C00 */
uint32_t icfgrn_rw; /* 0x0C04 */
uint32_t icfgr0; /* 0x0C00 */
uint32_t icfgr1; /* 0x0C04 */
uint32_t res9[62]; /* 0x0C08 */
uint32_t igrpmodr0; /* 0x0D00*/
uint32_t res10[63]; /* 0x0D04 */
uint32_t nsac; /* 0x0E00 */
uint32_t res11[11391]; /* 0x0E04 */
uint32_t miscstatsr; /* 0xC000 */
uint32_t res12[31]; /* 0xC004 */
uint32_t ppisr; /* 0xC080 */
uint32_t res13[4062]; /* 0xC084 */
uint32_t nsacr; /* 0x0E00 */
};
extern volatile struct gic_dist_map *const gic_dist;
......@@ -232,9 +210,9 @@ static inline int is_irq_edge_triggered(irq_t irq)
return 0;
}
if (is_ppi(irq)) {
icfgr = gic_rdist_sgi_ppi_map[CURRENT_CPU_INDEX()]->icfgrn_rw;
icfgr = gic_rdist_sgi_ppi_map[CURRENT_CPU_INDEX()]->icfgr1;
} else {
icfgr = gic_dist->config[word];
icfgr = gic_dist->icfgrn[word];
}
return !!(icfgr & BIT(bit + 1));
......@@ -249,7 +227,7 @@ static inline void gic_pending_clr(irq_t irq)
if (irq < NR_GIC_LOCAL_IRQS) {
gic_rdist_sgi_ppi_map[CURRENT_CPU_INDEX()]->icpendr0 = BIT(bit);
} else {
gic_dist->pending_clr[word] = BIT(bit);
gic_dist->icpendrn[word] = BIT(bit);
}
}
......@@ -261,7 +239,7 @@ static inline void gic_enable_clr(irq_t irq)
if (irq < NR_GIC_LOCAL_IRQS) {
gic_rdist_sgi_ppi_map[CURRENT_CPU_INDEX()]->icenabler0 = BIT(bit);
} else {
gic_dist->enable_clr[word] = BIT(bit);
gic_dist->icenablern[word] = BIT(bit);
}
}
......@@ -274,7 +252,7 @@ static inline void gic_enable_set(irq_t irq)
if (irq < NR_GIC_LOCAL_IRQS) {
gic_rdist_sgi_ppi_map[CURRENT_CPU_INDEX()]->isenabler0 = BIT(bit);
} else {
gic_dist->enable_set[word] = BIT(bit);
gic_dist->isenablern[word] = BIT(bit);
}
}
......
src/arch/arm/machine/gic_500.c
+ 6
− 6
View file @ 969c8b93
......@@ -136,19 +136,19 @@ BOOT_CODE static void dist_init(void)
/* Assume level-triggered */
for (i = NR_GIC_LOCAL_IRQS; i < nr_lines; i += 16) {
gic_dist->config[(i / 16)] = 0;
gic_dist->icfgrn[(i / 16)] = 0;
}
/* Default priority for global interrupts */
priority = (GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 | GIC_PRI_IRQ << 8 |
GIC_PRI_IRQ);
for (i = NR_GIC_LOCAL_IRQS; i < nr_lines; i += 4) {
gic_dist->priority[(i / 4)] = priority;
gic_dist->ipriorityrn[(i / 4)] = priority;
}
/* Disable and clear all global interrupts */
for (i = NR_GIC_LOCAL_IRQS; i < nr_lines; i += 32) {
gic_dist->enable_clr[(i / 32)] = IRQ_SET_ALL;
gic_dist->pending_clr[(i / 32)] = IRQ_SET_ALL;
gic_dist->icenablern[(i / 32)] = IRQ_SET_ALL;
gic_dist->icpendrn[(i / 32)] = IRQ_SET_ALL;
}
/* Turn on the distributor */
......@@ -158,7 +158,7 @@ BOOT_CODE static void dist_init(void)
/* Route all global IRQs to this CPU */
affinity = mpidr_to_gic_affinity();
for (i = NR_GIC_LOCAL_IRQS; i < nr_lines; i++) {
gic_dist->irouter[i] = affinity;
gic_dist->iroutern[i] = affinity;
}
}
......@@ -242,7 +242,7 @@ BOOT_CODE static void gicr_init(void)
gic_rdist_sgi_ppi_map[CURRENT_CPU_INDEX()]->isenabler0 = 0x0000ffff;
/* Set ICFGR1 for PPIs as level-triggered */
gic_rdist_sgi_ppi_map[CURRENT_CPU_INDEX()]->icfgrn_rw = 0x0;
gic_rdist_sgi_ppi_map[CURRENT_CPU_INDEX()]->icfgr1 = 0x0;
gicv3_redist_wait_for_rwp();
}
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment