Add initial i.MX8M Quad evk 64-bit Support

This adds support for the 64-bit i.MX8M Quad evaluation kit.
Currently only AArch64 EL1 is supported.

CHANGES

@@ -39,6 +39,7 @@ Upcoming release: BREAKING
 * Add managed TLS register for all platforms
 * Add configurable system call allowing userspace to set TLS register without capability on all platforms.
 * Non-hyp support added for Arm GICv3 interrupt controller.
+* Add initial i.MX8M Quad evk 64-bit Support. Currently only AArch64 EL1 non-secure is supported.
 
 ## Upgrade Notes
 ---

libsel4/sel4_plat_include/imx8mq-evk/sel4/plat/api/constants.h

+/*
+ * Copyright 2017, Data61
+ * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
+ * ABN 41 687 119 230.
+ *
+ * This software may be distributed and modified according to the terms of
+ * the BSD 2-Clause license. Note that NO WARRANTY is provided.
+ * See "LICENSE_BSD2.txt" for details.
+ *
+ * @TAG(DATA61_BSD)
+ */
+
+#ifndef __LIBSEL4_SEL4_PLAT_API_CONSTANTS_H_
+#define __LIBSEL4_SEL4_PLAT_API_CONSTANTS_H_
+
+#ifdef HAVE_AUTOCONF
+#include <autoconf.h>
+#endif
+
+#if CONFIG_WORD_SIZE == 32
+/* First address in the virtual address space that is not accessible to user level */
+#define seL4_UserTop 0xe0000000
+#else
+/* otherwise this is defined at the arch level */
+#endif
+
+#endif /* __LIBSEL4_SEL4_PLAT_API_CONSTANTS_H_ */

src/plat/imx8mq-evk/config.cmake

+#
+# Copyright 2019, Data61
+# Commonwealth Scientific and Industrial Research Organisation (CSIRO)
+# ABN 41 687 119 230.
+#
+# This software may be distributed and modified according to the terms of
+# the GNU General Public License version 2. Note that NO WARRANTY is provided.
+# See "LICENSE_GPLv2.txt" for details.
+#
+# @TAG(DATA61_GPL)
+#
+
+cmake_minimum_required(VERSION 3.7.2)
+
+declare_platform(imx8mq-evk KernelPlatformImx8mq-evk PLAT_IMX8MQ_EVK KernelSel4ArchAarch64)
+
+if(KernelPlatformImx8mq-evk)
+    declare_seL4_arch(aarch64)
+    set(KernelArmCortexA53 ON)
+    set(KernelArchArmV8a ON)
+    config_set(KernelARMPlatform PLAT "imx8mq-evk")
+    set(KernelArmMach "imx" CACHE INTERNAL "")
+    set(KernelArmPASizeBits40 ON)
+    list(APPEND KernelDTSList "tools/dts/imx8mq-evk.dts")
+    list(APPEND KernelDTSList "src/plat/imx8mq-evk/overlay-imx8m.dts")
+    declare_default_headers(
+        TIMER_FREQUENCY 8000000llu
+        MAX_IRQ 160
+        TIMER drivers/timer/arm_generic.h
+        INTERRUPT_CONTROLLER arch/machine/gic_v3.h
+    )
+endif()
+
+add_sources(
+    DEP "KernelPlatformImx8mq-evk"
+    CFILES src/arch/arm/machine/gic_v3.c src/arch/arm/machine/l2c_nop.c
+)

src/plat/imx8mq-evk/overlay-imx8m.dts

+/*
+ * Copyright 2018, Data61
+ * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
+ * ABN 41 687 119 230.
+ *
+ * This software may be distributed and modified according to the terms of
+ * the GNU General Public License version 2. Note that NO WARRANTY is provided.
+ * See "LICENSE_GPLv2.txt" for details.
+ *
+ * @TAG(DATA61_GPL)
+ */
+
+/ {
+
+	/* This device exists in the SOC documentation, but not in the DTS from Linux */
+	gpt@302e0000 {
+		compatible = "fsl,imx8mq-gpt\0fsl,imx7d-gpt";
+		reg = < 0x00 0x302e0000 0x00 0x10000 >;
+		interrupts = < 0x00 0x36 0x04 >;
+		clocks = < 0x04 0xc5 0x04 0xc5 0x04 0xf9 >;
+		clock-names = "ipg\0per\0osc_per";
+		status = "disabled";
+	};
+
+};
\ No newline at end of file

tools/dts/update-dts.sh

@@ -67,6 +67,7 @@ hisilicon/hi6220-hikey=hikey
 nvidia/tegra210-p2371-2180=tx1
 xilinx/avnet-ultra96-rev1=ultra96
 xilinx/zynqmp-zcu102-rev1.0=zynqmp
+freescale/fsl-imx8mq-evk=imx8mq-evk
 "
 
 extract_dts() {