`pragma clang fp eval_method`.

Differential Revision: https://reviews.llvm.org/D109239

Differential Revision: https://reviews.llvm.org/D119161

The RegionPrinter, RegionOnlyPrinter, RegionViewer and RegionOnlyViewer passes have not yet been ported to the new pass manager.

Reviewed By: aeubanks

Differential Revision: https://reviews.llvm.org/D119897

Aligned new does not require size to be a multiple of alignment, so
memalign is the correct choice instead of aligned_alloc.

Fixes false reports for unaligned sizes.

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D119161

Use case is offline evaluation (for inliner effectiveness) or debugging.

Differential Revision: https://reviews.llvm.org/D120344

Reviewed By: Quuxplusone, #libc

Spies: libcxx-commits

Differential Revision: https://reviews.llvm.org/D120141

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D119873

his patch adds builtins and intrinsics for the f16 and f16x2 variants of the ex2
instruction.

These two variants were added in PTX7.0, and are supported by sm_75 and above.

Note that this isn't wired with the exp2 llvm intrinsic because the ex2
instruction is only available in its approx variant.

Running ptxas on the assembly generated by the test f16-ex2.ll works as
expected.

Differential Revision: https://reviews.llvm.org/D119157

This patch adds builtins/intrinsics for the following variants of FMA:

- f16, f16x2
  - rn
  - rn_ftz
  - rn_sat
  - rn_ftz_sat
  - rn_relu
  - rn_ftz_relu
- bf16, bf16x2
  - rn
  - rn_relu

ptxas (Cuda compilation tools, release 11.0, V11.0.194) is happy with the generated assembly.

Differential Revision: https://reviews.llvm.org/D118977

Adds support for the following builtins:

- abs, neg:
- .bf16,
- .bf16x2
- min, max
- {.ftz}{.NaN}{.xorsign.abs}.f16
- {.ftz}{.NaN}{.xorsign.abs}.f16x2
- {.NaN}{.xorsign.abs}.bf16
- {.NaN}{.xorsign.abs}.bf16x2
- {.ftz}{.NaN}{.xorsign.abs}.f32

Differential Revision: https://reviews.llvm.org/D117887

Currently when we generate OpenMP offloading code we always make
fallback code for the CPU. This is necessary for implementing features
like conditional offloading and ensuring that unhandled pragmas don't
result in missing symbols. However, this is problematic for a few cases.
For offloading tests we can silently fail to the host without realizing
that offloading failed. Additionally, this makes it impossible to
provide interoperabiility to other offloading schemes like HIP or CUDA
because those methods do not provide any such host fallback guaruntee.
this patch adds the `-fopenmp-offload-mandatory` flag to prevent
generating the fallback symbol on the CPU and instead replaces the
function with a dummy global and the failed branch with 'unreachable'.

Reviewed By: ABataev

Differential Revision: https://reviews.llvm.org/D120353

An entire bundle must be inside the scheduling window.  Assert that this property holds as opposed to checking it at runtime.

The stack trace addresses may be odd (normally addresses should be even), but
seems a good compromise when the instruction length (2,4,6) cannot be detected
easily.

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D120432

Based on the discussion in D115393, I've updated the names to be more
descriptive.

Reviewed By: ellis, MaskRay

Differential Revision: https://reviews.llvm.org/D120092

This reverts commit 6adf4b03.  Reverting while investigating https://github.com/llvm/llvm-project/issues/54029

This reverts commit 8c85f3a0.

This matches the fixes for the wchar version in
f081cc50.

Differential Revision: https://reviews.llvm.org/D120283

Internally to DAGCombiner the SDValues were passed by non-const
reference despite not being modified. They were then passed by
const reference to TLI.

This patch passes them by value which is consistent with the vast
majority of code.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D120420

In combineCarryDiamond() use getAsCarry() to find more candidates for being a carry flag.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D118362

Fix window debug build.

Jim noticed that the regex command is unintentionally recursive. Let's
use the following command regex as an example:

  (lldb) com regex humm 's/([^ ]+) ([^ ]+)/p %1 %2 %1 %2/'

If we call it with arguments foo bar, thing behave as expected:

  (lldb) humm foo bar
  (...)
  foo bar foo bar

However, if we include %2 in the arguments, things break down:

  (lldb) humm fo%2o bar
  (...)
  fobaro bar fobaro bar

The problem is that the implementation of the substitution is too naive.
It substitutes the %1 token into the target template in place, then does
the %2 substitution starting with the resultant string. So if the
previous substitution introduced a %2 token, it would get processed in
the second sweep, etc.

This patch addresses the issue by walking the command once and
substituting the % variables in place.

  (lldb) humm fo%2o bar
  (...)
  fo%2o bar fo%2o bar

Furthermore, this patch also reports an error if not enough variables
were provided and add support for substituting %0.

rdar://81236994

Differential revision: https://reviews.llvm.org/D120101

This test doesn't work because the CHECK-NOT line is actually checking
something that only exists on stderr and not stdout.
Changed the test so that we now check both stderr and stdout.
Changed the test so that we check pwr9, pwr10, and future. The cpu names of
power9 or power10 are not supported in the llc backend.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D120349

By specifying a sectionMemoryMapper, users can control how
memory for JIT code is allocated.

In particular, I need this in order to use a named memory
region so that profilers such as perf(1) can correctly label
execution cycles coming from JIT'ed code.

Reviewed-by: ezhulenev

Differential Revision: https://reviews.llvm.org/D120415

It's customary for these options to have the -fno- form which is sometimes
handy to work around issues. Using the supported driver option is preferred over
the internal cl::opt option `-mllvm -asan-globals-live-support=0`

Reviewed By: kstoimenov, vitalybuka

Differential Revision: https://reviews.llvm.org/D120391

First step in trying to shrink the memory footprint of ScheduleData to improve cache locality.

Fixes:
https://bugs.llvm.org/show_bug.cgi?id=51641

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D115447

There should be 1-bit unused field between tid field and is_atomic field of Shadow.

Reviewed By: dvyukov, vitalybuka

Differential Revision: https://reviews.llvm.org/D119417

Wrong author.

This reverts commit 6bff092e.

This change uses instruction's comesBefore method to simplify the code significantly. There's little compile time concern here because getSpillCost already calls comesBefore on every basic block which contains a vectorization candidate. The only additional times we'll build basic block ordering is when we can't schedule a vector candidate anywhere in the containing block.

Differential Revision: https://reviews.llvm.org/D120364