[InstCombine] SimplifyDemandedUseBits - allow and(srem(X,Pow2),C) -> and(X,C)...

[InstCombine] SimplifyDemandedUseBits - allow and(srem(X,Pow2),C) -> and(X,C) to work on vector types

Replace m_ConstantInt with m_APInt to match uniform (no-undef) vector remainder amounts.

llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp

@@ -739,13 +739,13 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
     break;
   }
   case Instruction::SRem: {
-    ConstantInt *Rem;
-    if (match(I->getOperand(1), m_ConstantInt(Rem))) {
+    const APInt *Rem;
+    if (match(I->getOperand(1), m_APInt(Rem))) {
       // X % -1 demands all the bits because we don't want to introduce
       // INT_MIN % -1 (== undef) by accident.
-      if (Rem->isMinusOne())
+      if (Rem->isAllOnes())
         break;
-      APInt RA = Rem->getValue().abs();
+      APInt RA = Rem->abs();
       if (RA.isPowerOf2()) {
         if (DemandedMask.ult(RA))    // srem won't affect demanded bits
           return I->getOperand(0);

llvm/test/Transforms/InstCombine/2008-07-11-RemAnd.ll

@@ -17,9 +17,8 @@ entry:
 define <2 x i32> @a_vec(<2 x i32> %b) nounwind  {
 ; CHECK-LABEL: @a_vec(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = srem <2 x i32> [[B:%.*]], <i32 8, i32 8>
-; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> [[TMP0]], <i32 1, i32 1>
-; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
+; CHECK-NEXT:    [[TMP0:%.*]] = and <2 x i32> [[B:%.*]], <i32 1, i32 1>
+; CHECK-NEXT:    ret <2 x i32> [[TMP0]]
 ;
 entry:
   srem <2 x i32> %b, <i32 8, i32 8>