对-对旁路转发的模块化进行优化

generated/PiplineCPUwithBPandF/PiplineCPUwithBPandF.fir

@@ -1447,8 +1447,8 @@ circuit PiplineCPUwithBPandF :
     input reset : Reset
     output io : { flip keep : UInt<1>, flip ifMayJump : UInt<1>, flip ifPC : UInt<64>, flip idPC : UInt<64>, flip exePC : UInt<64>, flip idInst : UInt<32>, flip exeInst : UInt<32>, flip selectPC : UInt<64>, flip jump : UInt<1>, nextPC : UInt<64>, flush : UInt<1>}
 
-    cmem phtMem : UInt<2> [4096] @[BranchPredictor.scala 92:19]
-    cmem btbMem : UInt<128> [64] @[BranchPredictor.scala 107:19]
+    cmem phtMem : UInt<2> [4096] @[BranchPredictor.scala 94:19]
+    cmem btbMem : UInt<128> [64] @[BranchPredictor.scala 109:19]
     reg flushReg : UInt<1>, clock with :
       reset => (reset, UInt<1>("h0")) @[BranchPredictor.scala 40:25]
     node _nextPC_T = add(io.ifPC, UInt<3>("h4")) @[BranchPredictor.scala 42:36]
@@ -1465,72 +1465,104 @@ circuit PiplineCPUwithBPandF :
     else :
       when io.ifMayJump : @[BranchPredictor.scala 54:24]
         node _historyState_T = bits(ifPCIndex, 11, 0) @[BranchPredictor.scala 56:55]
-        read mport historyState = phtMem[_historyState_T], clock @[BranchPredictor.scala 95:16]
-        node _T = asUInt(reset) @[BranchPredictor.scala 57:13]
-        node _T_1 = eq(_T, UInt<1>("h0")) @[BranchPredictor.scala 57:13]
-        when _T_1 : @[BranchPredictor.scala 57:13]
-          printf(clock, UInt<1>("h1"), "[DEBUG] \u83B7\u53D6\u9971\u548C\u8BA1\u6570\u5668 : ifPC = %d, historyState = %d\n", io.ifPC, historyState) : printf @[BranchPredictor.scala 57:13]
-        node _T_2 = bits(historyState, 1, 1) @[BranchPredictor.scala 60:24]
-        node _T_3 = eq(_T_2, UInt<1>("h1")) @[BranchPredictor.scala 60:28]
-        when _T_3 : @[BranchPredictor.scala 60:37]
-          node _target_data_T = bits(ifPCIndex, 5, 0) @[BranchPredictor.scala 110:35]
-          read mport target_data = btbMem[_target_data_T], clock @[BranchPredictor.scala 110:27]
-          node target_pcSource = bits(target_data, 127, 64) @[BranchPredictor.scala 111:24]
-          node _target_target_T = add(ifPCIndex, UInt<1>("h1")) @[BranchPredictor.scala 112:38]
-          node _target_target_T_1 = tail(_target_target_T, 1) @[BranchPredictor.scala 112:38]
-          wire target_target : UInt
-          target_target <= _target_target_T_1
-          node _target_T = shr(target_pcSource, 2) @[BranchPredictor.scala 113:20]
-          node _target_T_1 = eq(_target_T, ifPCIndex) @[BranchPredictor.scala 113:43]
-          when _target_T_1 : @[BranchPredictor.scala 113:56]
-            node _target_target_T_2 = bits(target_data, 63, 0) @[BranchPredictor.scala 114:21]
-            target_target <= _target_target_T_2 @[BranchPredictor.scala 114:14]
-          node target = shl(target_target, 2) @[BranchPredictor.scala 116:12]
-          nextPC <= target @[BranchPredictor.scala 63:16]
-    node _T_4 = neq(io.idInst, UInt<1>("h0")) @[BranchPredictor.scala 70:16]
-    node _T_5 = neq(io.exeInst, UInt<1>("h0")) @[BranchPredictor.scala 70:40]
-    node _T_6 = and(_T_4, _T_5) @[BranchPredictor.scala 70:25]
-    node _T_7 = neq(io.idPC, io.selectPC) @[BranchPredictor.scala 70:61]
-    node _T_8 = and(_T_6, _T_7) @[BranchPredictor.scala 70:49]
-    when _T_8 : @[BranchPredictor.scala 71:5]
-      nextPC <= io.selectPC @[BranchPredictor.scala 72:12]
-      flushReg <= UInt<1>("h1") @[BranchPredictor.scala 73:14]
-    node _T_9 = bits(exePCIndex, 11, 0) @[BranchPredictor.scala 77:24]
-    read mport historyState_1 = phtMem[_T_9], clock @[BranchPredictor.scala 98:35]
-    node _T_10 = bits(historyState_1, 0, 0) @[BranchPredictor.scala 99:41]
-    node _T_11 = cat(_T_10, io.jump) @[Cat.scala 33:92]
-    write mport MPORT = phtMem[_T_9], clock
-    MPORT <= _T_11
-    node _T_12 = bits(exePCIndex, 11, 0) @[BranchPredictor.scala 78:38]
-    read mport MPORT_1 = phtMem[_T_12], clock @[BranchPredictor.scala 95:16]
-    node _T_13 = neq(MPORT_1, UInt<1>("h0")) @[BranchPredictor.scala 78:60]
-    when _T_13 : @[BranchPredictor.scala 78:69]
-      node _T_14 = asUInt(reset) @[BranchPredictor.scala 79:11]
-      node _T_15 = eq(_T_14, UInt<1>("h0")) @[BranchPredictor.scala 79:11]
-      when _T_15 : @[BranchPredictor.scala 79:11]
-        printf(clock, UInt<1>("h1"), "[DEBUG] \u66F4\u65B0\u9971\u548C\u8BA1\u6570\u5668 : exePC = %d, jump = %d\n", io.exePC, io.jump) : printf_1 @[BranchPredictor.scala 79:11]
-    when io.jump : @[BranchPredictor.scala 81:17]
-      node pcSource = shl(exePCIndex, 2) @[BranchPredictor.scala 120:28]
+        read mport historyState = phtMem[_historyState_T], clock @[BranchPredictor.scala 97:16]
+        node _T = bits(historyState, 1, 1) @[BranchPredictor.scala 60:24]
+        node _T_1 = eq(_T, UInt<1>("h1")) @[BranchPredictor.scala 60:28]
+        when _T_1 : @[BranchPredictor.scala 60:37]
+          node _target_data_T = bits(ifPCIndex, 5, 0) @[BranchPredictor.scala 112:35]
+          read mport target_data = btbMem[_target_data_T], clock @[BranchPredictor.scala 112:27]
+          node target_pcSource = bits(target_data, 127, 64) @[BranchPredictor.scala 113:24]
+          node _target_target_T = add(ifPCIndex, UInt<1>("h1")) @[BranchPredictor.scala 115:28]
+          node _target_target_T_1 = tail(_target_target_T, 1) @[BranchPredictor.scala 115:28]
+          node _target_target_T_2 = shl(_target_target_T_1, 2) @[BranchPredictor.scala 115:35]
+          wire target : UInt
+          target <= _target_target_T_2
+          node _target_T = shr(target_pcSource, 2) @[BranchPredictor.scala 116:20]
+          node _target_T_1 = eq(_target_T, ifPCIndex) @[BranchPredictor.scala 116:43]
+          when _target_T_1 : @[BranchPredictor.scala 116:56]
+            node _target_target_T_3 = bits(target_data, 63, 0) @[BranchPredictor.scala 117:21]
+            target <= _target_target_T_3 @[BranchPredictor.scala 117:14]
+          nextPC <= target @[BranchPredictor.scala 64:16]
+    node _T_2 = neq(io.idInst, UInt<1>("h0")) @[BranchPredictor.scala 71:16]
+    node _T_3 = neq(io.exeInst, UInt<1>("h0")) @[BranchPredictor.scala 71:40]
+    node _T_4 = and(_T_2, _T_3) @[BranchPredictor.scala 71:25]
+    node _T_5 = neq(io.idPC, io.selectPC) @[BranchPredictor.scala 71:61]
+    node _T_6 = and(_T_4, _T_5) @[BranchPredictor.scala 71:49]
+    when _T_6 : @[BranchPredictor.scala 72:5]
+      nextPC <= io.selectPC @[BranchPredictor.scala 73:12]
+      flushReg <= UInt<1>("h1") @[BranchPredictor.scala 74:14]
+    node _T_7 = bits(exePCIndex, 11, 0) @[BranchPredictor.scala 78:24]
+    read mport historyState_1 = phtMem[_T_7], clock @[BranchPredictor.scala 100:35]
+    node _T_8 = bits(historyState_1, 0, 0) @[BranchPredictor.scala 101:41]
+    node _T_9 = cat(_T_8, io.jump) @[Cat.scala 33:92]
+    write mport MPORT = phtMem[_T_7], clock
+    MPORT <= _T_9
+    when io.jump : @[BranchPredictor.scala 82:17]
+      node pcSource = shl(exePCIndex, 2) @[BranchPredictor.scala 123:28]
       node data = cat(pcSource, io.selectPC) @[Cat.scala 33:92]
-      node _T_16 = bits(exePCIndex, 5, 0) @[BranchPredictor.scala 122:25]
-      write mport MPORT_2 = btbMem[_T_16], clock
-      MPORT_2 <= data
-    io.nextPC <= nextPC @[BranchPredictor.scala 86:13]
-    io.flush <= flushReg @[BranchPredictor.scala 87:12]
+      node _T_10 = bits(exePCIndex, 5, 0) @[BranchPredictor.scala 125:25]
+      write mport MPORT_1 = btbMem[_T_10], clock
+      MPORT_1 <= data
+    io.nextPC <= nextPC @[BranchPredictor.scala 88:13]
+    io.flush <= flushReg @[BranchPredictor.scala 89:12]
 
-  module DataForwardingUnit :
+  module HazardJudgement :
+    input clock : Clock
+    input reset : Reset
+    output io : { flip pcRs1ToAlu : UInt<1>, flip rs1 : UInt<5>, flip memWrite : UInt<1>, flip immRs2ToAlu : UInt<1>, flip rs2 : UInt<5>, flip exeWriteEnable : UInt<1>, flip exeRd : UInt<5>, flip memWriteEnable : UInt<1>, flip memRd : UInt<5>, ifRS1EXE : UInt<1>, ifRS2EXE : UInt<1>, ifRS1MEM : UInt<1>, ifRS2MEM : UInt<1>}
+
+    wire useRs1 : UInt<5>
+    useRs1 <= UInt<5>("h0")
+    wire useRs2 : UInt<5>
+    useRs2 <= UInt<5>("h0")
+    wire exeWriteRd : UInt<5>
+    exeWriteRd <= UInt<5>("h0")
+    wire memWriteRd : UInt<5>
+    memWriteRd <= UInt<5>("h0")
+    node _T = eq(io.pcRs1ToAlu, UInt<1>("h0")) @[DataForwardingUnit.scala 45:22]
+    when _T : @[DataForwardingUnit.scala 45:35]
+      useRs1 <= io.rs1 @[DataForwardingUnit.scala 45:44]
+    node _T_1 = eq(io.immRs2ToAlu, UInt<1>("h0")) @[DataForwardingUnit.scala 46:23]
+    node _T_2 = eq(io.memWrite, UInt<1>("h1")) @[DataForwardingUnit.scala 46:50]
+    node _T_3 = or(_T_1, _T_2) @[DataForwardingUnit.scala 46:35]
+    when _T_3 : @[DataForwardingUnit.scala 46:62]
+      useRs2 <= io.rs2 @[DataForwardingUnit.scala 47:12]
+    node _T_4 = eq(io.exeWriteEnable, UInt<1>("h1")) @[DataForwardingUnit.scala 49:26]
+    when _T_4 : @[DataForwardingUnit.scala 49:38]
+      exeWriteRd <= io.exeRd @[DataForwardingUnit.scala 49:51]
+    node _T_5 = eq(io.memWriteEnable, UInt<1>("h1")) @[DataForwardingUnit.scala 50:26]
+    when _T_5 : @[DataForwardingUnit.scala 50:38]
+      memWriteRd <= io.memRd @[DataForwardingUnit.scala 50:51]
+    node _ifRS1EXE_T = neq(exeWriteRd, UInt<1>("h0")) @[DataForwardingUnit.scala 53:17]
+    node _ifRS1EXE_T_1 = eq(useRs1, exeWriteRd) @[DataForwardingUnit.scala 53:37]
+    node ifRS1EXE = and(_ifRS1EXE_T, _ifRS1EXE_T_1) @[DataForwardingUnit.scala 53:26]
+    node _ifRS2EXE_T = neq(exeWriteRd, UInt<1>("h0")) @[DataForwardingUnit.scala 55:17]
+    node _ifRS2EXE_T_1 = eq(useRs2, exeWriteRd) @[DataForwardingUnit.scala 55:37]
+    node ifRS2EXE = and(_ifRS2EXE_T, _ifRS2EXE_T_1) @[DataForwardingUnit.scala 55:26]
+    node _ifRS1MEM_T = neq(memWriteRd, UInt<1>("h0")) @[DataForwardingUnit.scala 58:17]
+    node _ifRS1MEM_T_1 = eq(useRs1, memWriteRd) @[DataForwardingUnit.scala 58:37]
+    node ifRS1MEM = and(_ifRS1MEM_T, _ifRS1MEM_T_1) @[DataForwardingUnit.scala 58:26]
+    node _ifRS2MEM_T = neq(memWriteRd, UInt<1>("h0")) @[DataForwardingUnit.scala 60:17]
+    node _ifRS2MEM_T_1 = eq(useRs2, memWriteRd) @[DataForwardingUnit.scala 60:37]
+    node ifRS2MEM = and(_ifRS2MEM_T, _ifRS2MEM_T_1) @[DataForwardingUnit.scala 60:26]
+    io.ifRS1EXE <= ifRS1EXE @[DataForwardingUnit.scala 62:15]
+    io.ifRS2EXE <= ifRS2EXE @[DataForwardingUnit.scala 63:15]
+    io.ifRS1MEM <= ifRS1MEM @[DataForwardingUnit.scala 64:15]
+    io.ifRS2MEM <= ifRS2MEM @[DataForwardingUnit.scala 65:15]
+
+  module DataForwarding :
     input clock : Clock
     input reset : Reset
-    output io : { flip inWriteEnable : UInt<1>, flip inRd : UInt<5>, flip inData : UInt<64>, flip pcRs1ToAlu : UInt<1>, flip rs1 : UInt<5>, flip memWrite : UInt<1>, flip immRs2ToAlu : UInt<1>, flip rs2 : UInt<5>, flip exeWriteEnable : UInt<1>, flip exeRd : UInt<5>, flip memWriteEnable : UInt<1>, flip memRd : UInt<5>, flip exeIsJump : UInt<1>, flip exeImmALUToReg : UInt<1>, flip exeMemRead : UInt<1>, flip exeALUResult : UInt<64>, flip exeImm : UInt<64>, flip memIsJump : UInt<1>, flip memImmALUToReg : UInt<1>, flip memMemRead : UInt<1>, flip memReadData : UInt<64>, flip memALUResult : UInt<64>, flip memImm : UInt<64>, flip exePC : UInt<64>, flip memPC : UInt<64>, writeEnable : UInt<1>, rd : UInt<5>, data : UInt<64>, keep : UInt<1>, stall : UInt<1>, flush : UInt<1>, forwardRs1 : UInt<1>, forwardRs2 : UInt<1>, forwardData1 : UInt<64>, forwardData2 : UInt<64>}
+    output io : { flip ifRS1EXE : UInt<1>, flip ifRS2EXE : UInt<1>, flip ifRS1MEM : UInt<1>, flip ifRS2MEM : UInt<1>, flip exeIsJump : UInt<1>, flip exeImmALUToReg : UInt<1>, flip exeMemRead : UInt<1>, flip exeALUResult : UInt<64>, flip exeImm : UInt<64>, flip memIsJump : UInt<1>, flip memImmALUToReg : UInt<1>, flip memMemRead : UInt<1>, flip memReadData : UInt<64>, flip memALUResult : UInt<64>, flip memImm : UInt<64>, flip exePC : UInt<64>, flip memPC : UInt<64>, keep : UInt<1>, stall : UInt<1>, flush : UInt<1>, forwardRs1 : UInt<1>, forwardRs2 : UInt<1>, forwardData1 : UInt<64>, forwardData2 : UInt<64>}
 
-    reg needAdd_0 : UInt<1>, clock with :
-      reset => (reset, UInt<1>("h0")) @[DataForwardingUnit.scala 75:25]
-    reg needAdd_1 : UInt<64>, clock with :
-      reset => (reset, UInt<64>("h0")) @[DataForwardingUnit.scala 76:28]
+    reg stateReg : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[DataForwardingUnit.scala 119:25]
+    reg pcRecordReg : UInt<64>, clock with :
+      reset => (reset, UInt<64>("h0")) @[DataForwardingUnit.scala 120:28]
     reg ifNeedRs1 : UInt<1>, clock with :
-      reset => (reset, UInt<1>("h0")) @[DataForwardingUnit.scala 77:26]
+      reset => (reset, UInt<1>("h0")) @[DataForwardingUnit.scala 121:26]
     reg ifNeedRs2 : UInt<1>, clock with :
-      reset => (reset, UInt<1>("h0")) @[DataForwardingUnit.scala 78:26]
+      reset => (reset, UInt<1>("h0")) @[DataForwardingUnit.scala 122:26]
     wire keep : UInt<1>
     keep <= UInt<1>("h0")
     wire stall : UInt<1>
@@ -1545,137 +1577,145 @@ circuit PiplineCPUwithBPandF :
     forwardData1 <= UInt<64>("h0")
     wire forwardData2 : UInt<64>
     forwardData2 <= UInt<64>("h0")
-    wire useRs1 : UInt<5>
-    useRs1 <= UInt<5>("h0")
-    wire useRs2 : UInt<5>
-    useRs2 <= UInt<5>("h0")
-    wire exeWriteRd : UInt<5>
-    exeWriteRd <= UInt<5>("h0")
-    wire memWriteRd : UInt<5>
-    memWriteRd <= UInt<5>("h0")
-    node _T = eq(io.pcRs1ToAlu, UInt<1>("h0")) @[DataForwardingUnit.scala 96:22]
-    when _T : @[DataForwardingUnit.scala 96:35]
-      useRs1 <= io.rs1 @[DataForwardingUnit.scala 96:44]
-    node _T_1 = eq(io.immRs2ToAlu, UInt<1>("h0")) @[DataForwardingUnit.scala 97:23]
-    node _T_2 = eq(io.memWrite, UInt<1>("h1")) @[DataForwardingUnit.scala 97:50]
-    node _T_3 = or(_T_1, _T_2) @[DataForwardingUnit.scala 97:35]
-    when _T_3 : @[DataForwardingUnit.scala 97:62]
-      useRs2 <= io.rs2 @[DataForwardingUnit.scala 98:12]
-    node _T_4 = eq(io.exeWriteEnable, UInt<1>("h1")) @[DataForwardingUnit.scala 100:26]
-    when _T_4 : @[DataForwardingUnit.scala 100:38]
-      exeWriteRd <= io.exeRd @[DataForwardingUnit.scala 100:51]
-    node _T_5 = eq(io.memWriteEnable, UInt<1>("h1")) @[DataForwardingUnit.scala 101:26]
-    when _T_5 : @[DataForwardingUnit.scala 101:38]
-      memWriteRd <= io.memRd @[DataForwardingUnit.scala 101:51]
-    node _ifRS1EXE_T = neq(exeWriteRd, UInt<1>("h0")) @[DataForwardingUnit.scala 104:17]
-    node _ifRS1EXE_T_1 = eq(useRs1, exeWriteRd) @[DataForwardingUnit.scala 104:37]
-    node ifRS1EXE = and(_ifRS1EXE_T, _ifRS1EXE_T_1) @[DataForwardingUnit.scala 104:26]
-    node _ifRS2EXE_T = neq(exeWriteRd, UInt<1>("h0")) @[DataForwardingUnit.scala 106:17]
-    node _ifRS2EXE_T_1 = eq(useRs2, exeWriteRd) @[DataForwardingUnit.scala 106:37]
-    node ifRS2EXE = and(_ifRS2EXE_T, _ifRS2EXE_T_1) @[DataForwardingUnit.scala 106:26]
-    node _ifRS1MEM_T = neq(memWriteRd, UInt<1>("h0")) @[DataForwardingUnit.scala 109:17]
-    node _ifRS1MEM_T_1 = eq(useRs1, memWriteRd) @[DataForwardingUnit.scala 109:37]
-    node ifRS1MEM = and(_ifRS1MEM_T, _ifRS1MEM_T_1) @[DataForwardingUnit.scala 109:26]
-    node _ifRS2MEM_T = neq(memWriteRd, UInt<1>("h0")) @[DataForwardingUnit.scala 111:17]
-    node _ifRS2MEM_T_1 = eq(useRs2, memWriteRd) @[DataForwardingUnit.scala 111:37]
-    node ifRS2MEM = and(_ifRS2MEM_T, _ifRS2MEM_T_1) @[DataForwardingUnit.scala 111:26]
     wire exeResWire : UInt
     exeResWire <= io.exeALUResult
-    node _T_6 = eq(io.exeIsJump, UInt<1>("h1")) @[DataForwardingUnit.scala 114:21]
-    when _T_6 : @[DataForwardingUnit.scala 114:33]
-      node _exeResWire_T = add(io.exePC, UInt<3>("h4")) @[DataForwardingUnit.scala 115:28]
-      node _exeResWire_T_1 = tail(_exeResWire_T, 1) @[DataForwardingUnit.scala 115:28]
-      exeResWire <= _exeResWire_T_1 @[DataForwardingUnit.scala 115:16]
+    node _T = eq(io.exeIsJump, UInt<1>("h1")) @[DataForwardingUnit.scala 134:21]
+    when _T : @[DataForwardingUnit.scala 134:33]
+      node _exeResWire_T = add(io.exePC, UInt<3>("h4")) @[DataForwardingUnit.scala 135:28]
+      node _exeResWire_T_1 = tail(_exeResWire_T, 1) @[DataForwardingUnit.scala 135:28]
+      exeResWire <= _exeResWire_T_1 @[DataForwardingUnit.scala 135:16]
     else :
-      node _T_7 = eq(io.exeImmALUToReg, UInt<1>("h1")) @[DataForwardingUnit.scala 116:32]
-      when _T_7 : @[DataForwardingUnit.scala 116:44]
-        exeResWire <= io.exeImm @[DataForwardingUnit.scala 117:16]
+      node _T_1 = eq(io.exeImmALUToReg, UInt<1>("h1")) @[DataForwardingUnit.scala 136:32]
+      when _T_1 : @[DataForwardingUnit.scala 136:44]
+        exeResWire <= io.exeImm @[DataForwardingUnit.scala 137:16]
     wire memResWire : UInt
     memResWire <= io.memALUResult
-    node _T_8 = eq(io.memMemRead, UInt<1>("h1")) @[DataForwardingUnit.scala 121:22]
-    when _T_8 : @[DataForwardingUnit.scala 121:34]
-      memResWire <= io.memReadData @[DataForwardingUnit.scala 122:16]
+    node _T_2 = eq(io.memMemRead, UInt<1>("h1")) @[DataForwardingUnit.scala 141:22]
+    when _T_2 : @[DataForwardingUnit.scala 141:34]
+      memResWire <= io.memReadData @[DataForwardingUnit.scala 142:16]
     else :
-      node _T_9 = eq(io.memIsJump, UInt<1>("h1")) @[DataForwardingUnit.scala 123:27]
-      when _T_9 : @[DataForwardingUnit.scala 123:39]
-        node _memResWire_T = add(io.memPC, UInt<3>("h4")) @[DataForwardingUnit.scala 124:28]
-        node _memResWire_T_1 = tail(_memResWire_T, 1) @[DataForwardingUnit.scala 124:28]
-        memResWire <= _memResWire_T_1 @[DataForwardingUnit.scala 124:16]
+      node _T_3 = eq(io.memIsJump, UInt<1>("h1")) @[DataForwardingUnit.scala 143:27]
+      when _T_3 : @[DataForwardingUnit.scala 143:39]
+        node _memResWire_T = add(io.memPC, UInt<3>("h4")) @[DataForwardingUnit.scala 144:28]
+        node _memResWire_T_1 = tail(_memResWire_T, 1) @[DataForwardingUnit.scala 144:28]
+        memResWire <= _memResWire_T_1 @[DataForwardingUnit.scala 144:16]
       else :
-        node _T_10 = eq(io.memImmALUToReg, UInt<1>("h1")) @[DataForwardingUnit.scala 125:32]
-        when _T_10 : @[DataForwardingUnit.scala 125:44]
-          memResWire <= io.memImm @[DataForwardingUnit.scala 126:16]
-    node _T_11 = eq(UInt<1>("h0"), needAdd_0) @[DataForwardingUnit.scala 130:20]
-    when _T_11 : @[DataForwardingUnit.scala 130:20]
-      keep <= UInt<1>("h0") @[DataForwardingUnit.scala 132:12]
-      stall <= UInt<1>("h0") @[DataForwardingUnit.scala 133:13]
-      flush <= UInt<1>("h0") @[DataForwardingUnit.scala 134:13]
-      ifNeedRs1 <= UInt<1>("h0") @[DataForwardingUnit.scala 135:17]
-      ifNeedRs2 <= UInt<1>("h0") @[DataForwardingUnit.scala 136:17]
-      node _T_12 = eq(ifRS1EXE, UInt<1>("h1")) @[DataForwardingUnit.scala 138:21]
-      when _T_12 : @[DataForwardingUnit.scala 138:33]
-        node _T_13 = eq(io.exeMemRead, UInt<1>("h1")) @[DataForwardingUnit.scala 139:28]
-        when _T_13 : @[DataForwardingUnit.scala 139:40]
-          ifNeedRs1 <= UInt<1>("h1") @[DataForwardingUnit.scala 140:21]
-          needAdd_1 <= io.exePC @[DataForwardingUnit.scala 141:23]
-          keep <= UInt<1>("h1") @[DataForwardingUnit.scala 142:16]
-          stall <= UInt<1>("h1") @[DataForwardingUnit.scala 143:17]
-          needAdd_0 <= UInt<1>("h1") @[DataForwardingUnit.scala 144:20]
+        node _T_4 = eq(io.memImmALUToReg, UInt<1>("h1")) @[DataForwardingUnit.scala 145:32]
+        when _T_4 : @[DataForwardingUnit.scala 145:44]
+          memResWire <= io.memImm @[DataForwardingUnit.scala 146:16]
+    node _T_5 = eq(UInt<1>("h0"), stateReg) @[DataForwardingUnit.scala 150:20]
+    when _T_5 : @[DataForwardingUnit.scala 150:20]
+      keep <= UInt<1>("h0") @[DataForwardingUnit.scala 152:12]
+      stall <= UInt<1>("h0") @[DataForwardingUnit.scala 153:13]
+      flush <= UInt<1>("h0") @[DataForwardingUnit.scala 154:13]
+      ifNeedRs1 <= UInt<1>("h0") @[DataForwardingUnit.scala 155:17]
+      ifNeedRs2 <= UInt<1>("h0") @[DataForwardingUnit.scala 156:17]
+      node _T_6 = eq(io.ifRS1EXE, UInt<1>("h1")) @[DataForwardingUnit.scala 158:24]
+      when _T_6 : @[DataForwardingUnit.scala 158:36]
+        node _T_7 = eq(io.exeMemRead, UInt<1>("h1")) @[DataForwardingUnit.scala 159:28]
+        when _T_7 : @[DataForwardingUnit.scala 159:40]
+          ifNeedRs1 <= UInt<1>("h1") @[DataForwardingUnit.scala 160:21]
+          pcRecordReg <= io.exePC @[DataForwardingUnit.scala 161:23]
+          keep <= UInt<1>("h1") @[DataForwardingUnit.scala 162:16]
+          stall <= UInt<1>("h1") @[DataForwardingUnit.scala 163:17]
+          stateReg <= UInt<1>("h1") @[DataForwardingUnit.scala 164:20]
         else :
-          forwardData1 <= exeResWire @[DataForwardingUnit.scala 147:24]
-          forwardRs1 <= UInt<1>("h1") @[DataForwardingUnit.scala 148:22]
+          forwardData1 <= exeResWire @[DataForwardingUnit.scala 167:24]
+          forwardRs1 <= UInt<1>("h1") @[DataForwardingUnit.scala 168:22]
       else :
-        node _T_14 = eq(ifRS1MEM, UInt<1>("h1")) @[DataForwardingUnit.scala 151:23]
-        when _T_14 : @[DataForwardingUnit.scala 151:35]
-          forwardData1 <= memResWire @[DataForwardingUnit.scala 152:24]
-          forwardRs1 <= UInt<1>("h1") @[DataForwardingUnit.scala 153:22]
-      node _T_15 = eq(ifRS2EXE, UInt<1>("h1")) @[DataForwardingUnit.scala 157:21]
-      when _T_15 : @[DataForwardingUnit.scala 157:33]
-        node _T_16 = eq(io.exeMemRead, UInt<1>("h1")) @[DataForwardingUnit.scala 158:28]
-        when _T_16 : @[DataForwardingUnit.scala 158:40]
-          ifNeedRs2 <= UInt<1>("h1") @[DataForwardingUnit.scala 159:21]
-          needAdd_1 <= io.exePC @[DataForwardingUnit.scala 160:23]
-          keep <= UInt<1>("h1") @[DataForwardingUnit.scala 161:16]
-          stall <= UInt<1>("h1") @[DataForwardingUnit.scala 162:17]
-          needAdd_0 <= UInt<1>("h1") @[DataForwardingUnit.scala 163:20]
+        node _T_8 = eq(io.ifRS1MEM, UInt<1>("h1")) @[DataForwardingUnit.scala 171:26]
+        when _T_8 : @[DataForwardingUnit.scala 171:38]
+          forwardData1 <= memResWire @[DataForwardingUnit.scala 172:24]
+          forwardRs1 <= UInt<1>("h1") @[DataForwardingUnit.scala 173:22]
+      node _T_9 = eq(io.ifRS2EXE, UInt<1>("h1")) @[DataForwardingUnit.scala 177:24]
+      when _T_9 : @[DataForwardingUnit.scala 177:36]
+        node _T_10 = eq(io.exeMemRead, UInt<1>("h1")) @[DataForwardingUnit.scala 178:28]
+        when _T_10 : @[DataForwardingUnit.scala 178:40]
+          ifNeedRs2 <= UInt<1>("h1") @[DataForwardingUnit.scala 179:21]
+          pcRecordReg <= io.exePC @[DataForwardingUnit.scala 180:23]
+          keep <= UInt<1>("h1") @[DataForwardingUnit.scala 181:16]
+          stall <= UInt<1>("h1") @[DataForwardingUnit.scala 182:17]
+          stateReg <= UInt<1>("h1") @[DataForwardingUnit.scala 183:20]
         else :
-          forwardData2 <= exeResWire @[DataForwardingUnit.scala 166:24]
-          forwardRs2 <= UInt<1>("h1") @[DataForwardingUnit.scala 167:22]
+          forwardData2 <= exeResWire @[DataForwardingUnit.scala 186:24]
+          forwardRs2 <= UInt<1>("h1") @[DataForwardingUnit.scala 187:22]
       else :
-        node _T_17 = eq(ifRS2MEM, UInt<1>("h1")) @[DataForwardingUnit.scala 170:23]
-        when _T_17 : @[DataForwardingUnit.scala 170:35]
-          forwardData2 <= memResWire @[DataForwardingUnit.scala 171:24]
-          forwardRs2 <= UInt<1>("h1") @[DataForwardingUnit.scala 172:22]
+        node _T_11 = eq(io.ifRS2MEM, UInt<1>("h1")) @[DataForwardingUnit.scala 190:26]
+        when _T_11 : @[DataForwardingUnit.scala 190:38]
+          forwardData2 <= memResWire @[DataForwardingUnit.scala 191:24]
+          forwardRs2 <= UInt<1>("h1") @[DataForwardingUnit.scala 192:22]
     else :
-      node _T_18 = eq(UInt<1>("h1"), needAdd_0) @[DataForwardingUnit.scala 130:20]
-      when _T_18 : @[DataForwardingUnit.scala 130:20]
-        keep <= UInt<1>("h1") @[DataForwardingUnit.scala 178:12]
-        stall <= UInt<1>("h1") @[DataForwardingUnit.scala 179:13]
-        flush <= UInt<1>("h1") @[DataForwardingUnit.scala 180:13]
-        node _T_19 = eq(io.memPC, needAdd_1) @[DataForwardingUnit.scala 182:21]
-        when _T_19 : @[DataForwardingUnit.scala 182:38]
-          node _T_20 = eq(ifNeedRs1, UInt<1>("h1")) @[DataForwardingUnit.scala 183:24]
-          when _T_20 : @[DataForwardingUnit.scala 183:36]
-            forwardData1 <= memResWire @[DataForwardingUnit.scala 184:24]
-            forwardRs1 <= UInt<1>("h1") @[DataForwardingUnit.scala 185:22]
-          node _T_21 = eq(ifNeedRs2, UInt<1>("h1")) @[DataForwardingUnit.scala 187:24]
-          when _T_21 : @[DataForwardingUnit.scala 187:36]
-            forwardData2 <= memResWire @[DataForwardingUnit.scala 188:24]
-            forwardRs2 <= UInt<1>("h1") @[DataForwardingUnit.scala 189:22]
-          needAdd_1 <= UInt<1>("h0") @[DataForwardingUnit.scala 192:21]
-          keep <= UInt<1>("h0") @[DataForwardingUnit.scala 193:14]
-          stall <= UInt<1>("h0") @[DataForwardingUnit.scala 194:15]
-          needAdd_0 <= UInt<1>("h0") @[DataForwardingUnit.scala 195:18]
-    io.keep <= keep @[DataForwardingUnit.scala 200:11]
-    io.stall <= stall @[DataForwardingUnit.scala 201:12]
-    io.flush <= flush @[DataForwardingUnit.scala 202:12]
-    io.forwardRs1 <= forwardRs1 @[DataForwardingUnit.scala 204:17]
-    io.forwardRs2 <= forwardRs2 @[DataForwardingUnit.scala 205:17]
-    io.forwardData1 <= forwardData1 @[DataForwardingUnit.scala 206:19]
-    io.forwardData2 <= forwardData2 @[DataForwardingUnit.scala 207:19]
-    io.writeEnable <= io.inWriteEnable @[DataForwardingUnit.scala 210:18]
-    io.rd <= io.inRd @[DataForwardingUnit.scala 211:9]
-    io.data <= io.inData @[DataForwardingUnit.scala 212:11]
+      node _T_12 = eq(UInt<1>("h1"), stateReg) @[DataForwardingUnit.scala 150:20]
+      when _T_12 : @[DataForwardingUnit.scala 150:20]
+        keep <= UInt<1>("h1") @[DataForwardingUnit.scala 198:12]
+        stall <= UInt<1>("h1") @[DataForwardingUnit.scala 199:13]
+        flush <= UInt<1>("h1") @[DataForwardingUnit.scala 200:13]
+        node _T_13 = eq(io.memPC, pcRecordReg) @[DataForwardingUnit.scala 202:21]
+        when _T_13 : @[DataForwardingUnit.scala 202:38]
+          node _T_14 = eq(ifNeedRs1, UInt<1>("h1")) @[DataForwardingUnit.scala 203:24]
+          when _T_14 : @[DataForwardingUnit.scala 203:36]
+            forwardData1 <= memResWire @[DataForwardingUnit.scala 204:24]
+            forwardRs1 <= UInt<1>("h1") @[DataForwardingUnit.scala 205:22]
+          node _T_15 = eq(ifNeedRs2, UInt<1>("h1")) @[DataForwardingUnit.scala 207:24]
+          when _T_15 : @[DataForwardingUnit.scala 207:36]
+            forwardData2 <= memResWire @[DataForwardingUnit.scala 208:24]
+            forwardRs2 <= UInt<1>("h1") @[DataForwardingUnit.scala 209:22]
+          pcRecordReg <= UInt<1>("h0") @[DataForwardingUnit.scala 212:21]
+          keep <= UInt<1>("h0") @[DataForwardingUnit.scala 213:14]
+          stall <= UInt<1>("h0") @[DataForwardingUnit.scala 214:15]
+          stateReg <= UInt<1>("h0") @[DataForwardingUnit.scala 215:18]
+    io.keep <= keep @[DataForwardingUnit.scala 220:11]
+    io.stall <= stall @[DataForwardingUnit.scala 221:12]
+    io.flush <= flush @[DataForwardingUnit.scala 222:12]
+    io.forwardRs1 <= forwardRs1 @[DataForwardingUnit.scala 224:17]
+    io.forwardRs2 <= forwardRs2 @[DataForwardingUnit.scala 225:17]
+    io.forwardData1 <= forwardData1 @[DataForwardingUnit.scala 226:19]
+    io.forwardData2 <= forwardData2 @[DataForwardingUnit.scala 227:19]
+
+  module DataForwardingUnit :
+    input clock : Clock
+    input reset : Reset
+    output io : { flip pcRs1ToAlu : UInt<1>, flip rs1 : UInt<5>, flip memWrite : UInt<1>, flip immRs2ToAlu : UInt<1>, flip rs2 : UInt<5>, flip exeWriteEnable : UInt<1>, flip exeRd : UInt<5>, flip memWriteEnable : UInt<1>, flip memRd : UInt<5>, flip exeIsJump : UInt<1>, flip exeImmALUToReg : UInt<1>, flip exeMemRead : UInt<1>, flip exeALUResult : UInt<64>, flip exeImm : UInt<64>, flip memIsJump : UInt<1>, flip memImmALUToReg : UInt<1>, flip memMemRead : UInt<1>, flip memReadData : UInt<64>, flip memALUResult : UInt<64>, flip memImm : UInt<64>, flip exePC : UInt<64>, flip memPC : UInt<64>, keep : UInt<1>, stall : UInt<1>, flush : UInt<1>, forwardRs1 : UInt<1>, forwardRs2 : UInt<1>, forwardData1 : UInt<64>, forwardData2 : UInt<64>}
+
+    inst hazardJudgement of HazardJudgement @[DataForwardingUnit.scala 283:31]
+    hazardJudgement.clock <= clock
+    hazardJudgement.reset <= reset
+    inst dataForwarding of DataForwarding @[DataForwardingUnit.scala 284:30]
+    dataForwarding.clock <= clock
+    dataForwarding.reset <= reset
+    hazardJudgement.io.pcRs1ToAlu <= io.pcRs1ToAlu @[DataForwardingUnit.scala 286:33]
+    hazardJudgement.io.rs1 <= io.rs1 @[DataForwardingUnit.scala 287:26]
+    hazardJudgement.io.memWrite <= io.memWrite @[DataForwardingUnit.scala 288:31]
+    hazardJudgement.io.immRs2ToAlu <= io.immRs2ToAlu @[DataForwardingUnit.scala 289:34]
+    hazardJudgement.io.rs2 <= io.rs2 @[DataForwardingUnit.scala 290:26]
+    hazardJudgement.io.exeWriteEnable <= io.exeWriteEnable @[DataForwardingUnit.scala 291:37]
+    hazardJudgement.io.exeRd <= io.exeRd @[DataForwardingUnit.scala 292:28]
+    hazardJudgement.io.memWriteEnable <= io.memWriteEnable @[DataForwardingUnit.scala 293:37]
+    hazardJudgement.io.memRd <= io.memRd @[DataForwardingUnit.scala 294:28]
+    dataForwarding.io.ifRS1EXE <= hazardJudgement.io.ifRS1EXE @[DataForwardingUnit.scala 296:30]
+    dataForwarding.io.ifRS2EXE <= hazardJudgement.io.ifRS2EXE @[DataForwardingUnit.scala 297:30]
+    dataForwarding.io.ifRS1MEM <= hazardJudgement.io.ifRS1MEM @[DataForwardingUnit.scala 298:30]
+    dataForwarding.io.ifRS2MEM <= hazardJudgement.io.ifRS2MEM @[DataForwardingUnit.scala 299:30]
+    dataForwarding.io.exeIsJump <= io.exeIsJump @[DataForwardingUnit.scala 301:31]
+    dataForwarding.io.exeImmALUToReg <= io.exeImmALUToReg @[DataForwardingUnit.scala 302:36]
+    dataForwarding.io.exeMemRead <= io.exeMemRead @[DataForwardingUnit.scala 303:32]
+    dataForwarding.io.exeALUResult <= io.exeALUResult @[DataForwardingUnit.scala 304:34]
+    dataForwarding.io.exeImm <= io.exeImm @[DataForwardingUnit.scala 305:28]
+    dataForwarding.io.memIsJump <= io.memIsJump @[DataForwardingUnit.scala 307:31]
+    dataForwarding.io.memImmALUToReg <= io.memImmALUToReg @[DataForwardingUnit.scala 308:36]
+    dataForwarding.io.memMemRead <= io.memMemRead @[DataForwardingUnit.scala 309:32]
+    dataForwarding.io.memReadData <= io.memReadData @[DataForwardingUnit.scala 310:33]
+    dataForwarding.io.memALUResult <= io.memALUResult @[DataForwardingUnit.scala 311:34]
+    dataForwarding.io.memImm <= io.memImm @[DataForwardingUnit.scala 312:28]
+    dataForwarding.io.exePC <= io.exePC @[DataForwardingUnit.scala 314:27]
+    dataForwarding.io.memPC <= io.memPC @[DataForwardingUnit.scala 315:27]
+    io.keep <= dataForwarding.io.keep @[DataForwardingUnit.scala 317:11]
+    io.stall <= dataForwarding.io.stall @[DataForwardingUnit.scala 318:12]
+    io.flush <= dataForwarding.io.flush @[DataForwardingUnit.scala 319:12]
+    io.forwardRs1 <= dataForwarding.io.forwardRs1 @[DataForwardingUnit.scala 321:17]
+    io.forwardRs2 <= dataForwarding.io.forwardRs2 @[DataForwardingUnit.scala 322:17]
+    io.forwardData1 <= dataForwarding.io.forwardData1 @[DataForwardingUnit.scala 323:19]
+    io.forwardData2 <= dataForwarding.io.forwardData2 @[DataForwardingUnit.scala 324:19]
 
   module PiplineCPUwithBPandF :
     input clock : Clock
@@ -1878,74 +1918,71 @@ circuit PiplineCPUwithBPandF :
     branchPredictor.io.exeInst <= idEXEStageRegs.io.out.inst @[PiplineCPUwithBPandF.scala 187:30]
     branchPredictor.io.selectPC <= pcSelectUnit.io.nextPC @[PiplineCPUwithBPandF.scala 188:31]
     branchPredictor.io.jump <= pcSelectUnit.io.jump @[PiplineCPUwithBPandF.scala 189:27]
-    dataForwardingUnit.io.inWriteEnable <= memWBStageRegs.io.out.writeEnable @[PiplineCPUwithBPandF.scala 191:39]
-    dataForwardingUnit.io.inRd <= wbRd @[PiplineCPUwithBPandF.scala 192:30]
-    dataForwardingUnit.io.inData <= resSelectUnit.io.out @[PiplineCPUwithBPandF.scala 193:32]
-    dataForwardingUnit.io.pcRs1ToAlu <= controlUnit.io.pcRs1ToALU @[PiplineCPUwithBPandF.scala 194:36]
-    dataForwardingUnit.io.rs1 <= rs1 @[PiplineCPUwithBPandF.scala 195:29]
-    dataForwardingUnit.io.memWrite <= controlUnit.io.memWrite @[PiplineCPUwithBPandF.scala 196:34]
-    dataForwardingUnit.io.immRs2ToAlu <= controlUnit.io.immRs2ToALU @[PiplineCPUwithBPandF.scala 197:37]
-    dataForwardingUnit.io.rs2 <= rs2 @[PiplineCPUwithBPandF.scala 198:29]
-    dataForwardingUnit.io.exeWriteEnable <= idEXEStageRegs.io.out.writeEnable @[PiplineCPUwithBPandF.scala 199:40]
-    dataForwardingUnit.io.exeRd <= idEXEStageRegs.io.out.rd @[PiplineCPUwithBPandF.scala 200:31]
-    dataForwardingUnit.io.memWriteEnable <= exeMEMStageRegs.io.out.writeEnable @[PiplineCPUwithBPandF.scala 201:40]
-    dataForwardingUnit.io.memRd <= exeMEMStageRegs.io.out.rd @[PiplineCPUwithBPandF.scala 202:31]
-    dataForwardingUnit.io.exeIsJump <= idEXEStageRegs.io.out.isJump @[PiplineCPUwithBPandF.scala 204:35]
-    dataForwardingUnit.io.exeImmALUToReg <= idEXEStageRegs.io.out.immALUToReg @[PiplineCPUwithBPandF.scala 205:40]
-    dataForwardingUnit.io.exeMemRead <= idEXEStageRegs.io.out.memRead @[PiplineCPUwithBPandF.scala 206:36]
-    dataForwardingUnit.io.exeALUResult <= alu.io.result @[PiplineCPUwithBPandF.scala 207:38]
-    dataForwardingUnit.io.exeImm <= idEXEStageRegs.io.out.imm @[PiplineCPUwithBPandF.scala 208:32]
-    dataForwardingUnit.io.memIsJump <= exeMEMStageRegs.io.out.isJump @[PiplineCPUwithBPandF.scala 210:35]
-    dataForwardingUnit.io.memImmALUToReg <= exeMEMStageRegs.io.out.immALUToReg @[PiplineCPUwithBPandF.scala 211:40]
-    dataForwardingUnit.io.memMemRead <= exeMEMStageRegs.io.out.memRead @[PiplineCPUwithBPandF.scala 212:36]
-    dataForwardingUnit.io.memReadData <= dataMemory.io.readData @[PiplineCPUwithBPandF.scala 213:37]
-    dataForwardingUnit.io.memALUResult <= exeMEMStageRegs.io.out.aluResult @[PiplineCPUwithBPandF.scala 214:38]
-    dataForwardingUnit.io.memImm <= exeMEMStageRegs.io.out.imm @[PiplineCPUwithBPandF.scala 215:32]
-    dataForwardingUnit.io.exePC <= idEXEStageRegs.io.out.pc @[PiplineCPUwithBPandF.scala 217:31]
-    dataForwardingUnit.io.memPC <= exeMEMStageRegs.io.out.pc @[PiplineCPUwithBPandF.scala 218:31]
-    pcReg.io.in <= branchPredictor.io.nextPC @[PiplineCPUwithBPandF.scala 220:15]
-    instMemory.io.address <= pcReg.io.out @[PiplineCPUwithBPandF.scala 222:25]
-    controlUnit.io.opcode <= opcode @[PiplineCPUwithBPandF.scala 224:25]
-    aluControlUnit.io.isBType <= controlUnit.io.isBType @[PiplineCPUwithBPandF.scala 226:29]
-    aluControlUnit.io.isIType <= controlUnit.io.isIType @[PiplineCPUwithBPandF.scala 227:29]
-    aluControlUnit.io.isRType <= controlUnit.io.isRType @[PiplineCPUwithBPandF.scala 228:29]
-    aluControlUnit.io.isWord <= controlUnit.io.isWord @[PiplineCPUwithBPandF.scala 229:28]
-    aluControlUnit.io.funct3 <= funct3 @[PiplineCPUwithBPandF.scala 230:28]
-    aluControlUnit.io.funct7 <= funct7 @[PiplineCPUwithBPandF.scala 231:28]
-    regUnit.io.writeEnable <= dataForwardingUnit.io.writeEnable @[PiplineCPUwithBPandF.scala 233:26]
-    regUnit.io.rs1 <= rs1 @[PiplineCPUwithBPandF.scala 234:18]
-    regUnit.io.rs2 <= rs2 @[PiplineCPUwithBPandF.scala 235:18]
-    regUnit.io.rd <= dataForwardingUnit.io.rd @[PiplineCPUwithBPandF.scala 236:17]
-    regUnit.io.writeData <= dataForwardingUnit.io.data @[PiplineCPUwithBPandF.scala 237:24]
-    inst2ImmUnit.io.inst <= ifIDStageRegs.io.out.inst @[PiplineCPUwithBPandF.scala 239:24]
-    node _pcSelectUnit_io_pcPlus4_T = add(idEXEStageRegs.io.out.pc, UInt<3>("h4")) @[PiplineCPUwithBPandF.scala 241:36]
-    node _pcSelectUnit_io_pcPlus4_T_1 = tail(_pcSelectUnit_io_pcPlus4_T, 1) @[PiplineCPUwithBPandF.scala 241:36]
-    pcSelectUnit.io.pcPlus4 <= _pcSelectUnit_io_pcPlus4_T_1 @[PiplineCPUwithBPandF.scala 241:27]
-    node _pcSelectUnit_io_pcPlusImm_T = add(idEXEStageRegs.io.out.pc, idEXEStageRegs.io.out.imm) @[PiplineCPUwithBPandF.scala 242:38]
-    node _pcSelectUnit_io_pcPlusImm_T_1 = tail(_pcSelectUnit_io_pcPlusImm_T, 1) @[PiplineCPUwithBPandF.scala 242:38]
-    pcSelectUnit.io.pcPlusImm <= _pcSelectUnit_io_pcPlusImm_T_1 @[PiplineCPUwithBPandF.scala 242:29]
-    pcSelectUnit.io.isJALR <= idEXEStageRegs.io.out.isJALR @[PiplineCPUwithBPandF.scala 243:26]
-    pcSelectUnit.io.isBType <= idEXEStageRegs.io.out.isBType @[PiplineCPUwithBPandF.scala 244:27]
-    pcSelectUnit.io.isJump <= idEXEStageRegs.io.out.isJump @[PiplineCPUwithBPandF.scala 245:26]
-    node _pcSelectUnit_io_isTrue_T = bits(alu.io.result, 0, 0) @[PiplineCPUwithBPandF.scala 246:42]
-    pcSelectUnit.io.isTrue <= _pcSelectUnit_io_isTrue_T @[PiplineCPUwithBPandF.scala 246:26]
-    pcSelectUnit.io.aluResult <= alu.io.result @[PiplineCPUwithBPandF.scala 247:29]
-    alu.io.aluOperation <= idEXEStageRegs.io.out.aluOperation @[PiplineCPUwithBPandF.scala 249:23]
-    alu.io.x <= idEXEStageRegs.io.out.aluX @[PiplineCPUwithBPandF.scala 250:12]
-    alu.io.y <= idEXEStageRegs.io.out.aluY @[PiplineCPUwithBPandF.scala 251:12]
-    dataMemory.io.memRead <= exeMEMStageRegs.io.out.memRead @[PiplineCPUwithBPandF.scala 253:25]
-    dataMemory.io.memWrite <= exeMEMStageRegs.io.out.memWrite @[PiplineCPUwithBPandF.scala 254:26]
-    dataMemory.io.address <= exeMEMStageRegs.io.out.aluResult @[PiplineCPUwithBPandF.scala 255:25]
-    dataMemory.io.writeData <= exeMEMStageRegs.io.out.readDataRs2 @[PiplineCPUwithBPandF.scala 256:27]
-    dataMemory.io.bitType <= bitType @[PiplineCPUwithBPandF.scala 257:25]
-    dataMemory.io.isUnsigned <= isUnsigned @[PiplineCPUwithBPandF.scala 258:28]
-    resSelectUnit.io.isJump <= memWBStageRegs.io.out.isJump @[PiplineCPUwithBPandF.scala 260:27]
-    resSelectUnit.io.immALUToReg <= memWBStageRegs.io.out.immALUToReg @[PiplineCPUwithBPandF.scala 261:32]
-    resSelectUnit.io.memRead <= memWBStageRegs.io.out.memRead @[PiplineCPUwithBPandF.scala 262:28]
-    resSelectUnit.io.readData <= memWBStageRegs.io.out.readData @[PiplineCPUwithBPandF.scala 263:29]
-    resSelectUnit.io.aluResult <= memWBStageRegs.io.out.aluResult @[PiplineCPUwithBPandF.scala 264:30]
-    resSelectUnit.io.imm <= memWBStageRegs.io.out.imm @[PiplineCPUwithBPandF.scala 265:24]
-    node _resSelectUnit_io_pcPlus4_T = add(memWBStageRegs.io.out.pc, UInt<3>("h4")) @[PiplineCPUwithBPandF.scala 266:36]
-    node _resSelectUnit_io_pcPlus4_T_1 = tail(_resSelectUnit_io_pcPlus4_T, 1) @[PiplineCPUwithBPandF.scala 266:36]
-    resSelectUnit.io.pcPlus4 <= _resSelectUnit_io_pcPlus4_T_1 @[PiplineCPUwithBPandF.scala 266:28]
+    dataForwardingUnit.io.pcRs1ToAlu <= controlUnit.io.pcRs1ToALU @[PiplineCPUwithBPandF.scala 191:36]
+    dataForwardingUnit.io.rs1 <= rs1 @[PiplineCPUwithBPandF.scala 192:29]
+    dataForwardingUnit.io.memWrite <= controlUnit.io.memWrite @[PiplineCPUwithBPandF.scala 193:34]
+    dataForwardingUnit.io.immRs2ToAlu <= controlUnit.io.immRs2ToALU @[PiplineCPUwithBPandF.scala 194:37]
+    dataForwardingUnit.io.rs2 <= rs2 @[PiplineCPUwithBPandF.scala 195:29]
+    dataForwardingUnit.io.exeWriteEnable <= idEXEStageRegs.io.out.writeEnable @[PiplineCPUwithBPandF.scala 196:40]
+    dataForwardingUnit.io.exeRd <= idEXEStageRegs.io.out.rd @[PiplineCPUwithBPandF.scala 197:31]
+    dataForwardingUnit.io.memWriteEnable <= exeMEMStageRegs.io.out.writeEnable @[PiplineCPUwithBPandF.scala 198:40]
+    dataForwardingUnit.io.memRd <= exeMEMStageRegs.io.out.rd @[PiplineCPUwithBPandF.scala 199:31]
+    dataForwardingUnit.io.exeIsJump <= idEXEStageRegs.io.out.isJump @[PiplineCPUwithBPandF.scala 201:35]
+    dataForwardingUnit.io.exeImmALUToReg <= idEXEStageRegs.io.out.immALUToReg @[PiplineCPUwithBPandF.scala 202:40]
+    dataForwardingUnit.io.exeMemRead <= idEXEStageRegs.io.out.memRead @[PiplineCPUwithBPandF.scala 203:36]
+    dataForwardingUnit.io.exeALUResult <= alu.io.result @[PiplineCPUwithBPandF.scala 204:38]
+    dataForwardingUnit.io.exeImm <= idEXEStageRegs.io.out.imm @[PiplineCPUwithBPandF.scala 205:32]
+    dataForwardingUnit.io.memIsJump <= exeMEMStageRegs.io.out.isJump @[PiplineCPUwithBPandF.scala 207:35]
+    dataForwardingUnit.io.memImmALUToReg <= exeMEMStageRegs.io.out.immALUToReg @[PiplineCPUwithBPandF.scala 208:40]
+    dataForwardingUnit.io.memMemRead <= exeMEMStageRegs.io.out.memRead @[PiplineCPUwithBPandF.scala 209:36]
+    dataForwardingUnit.io.memReadData <= dataMemory.io.readData @[PiplineCPUwithBPandF.scala 210:37]
+    dataForwardingUnit.io.memALUResult <= exeMEMStageRegs.io.out.aluResult @[PiplineCPUwithBPandF.scala 211:38]
+    dataForwardingUnit.io.memImm <= exeMEMStageRegs.io.out.imm @[PiplineCPUwithBPandF.scala 212:32]
+    dataForwardingUnit.io.exePC <= idEXEStageRegs.io.out.pc @[PiplineCPUwithBPandF.scala 214:31]
+    dataForwardingUnit.io.memPC <= exeMEMStageRegs.io.out.pc @[PiplineCPUwithBPandF.scala 215:31]
+    pcReg.io.in <= branchPredictor.io.nextPC @[PiplineCPUwithBPandF.scala 217:15]
+    instMemory.io.address <= pcReg.io.out @[PiplineCPUwithBPandF.scala 219:25]
+    controlUnit.io.opcode <= opcode @[PiplineCPUwithBPandF.scala 221:25]
+    aluControlUnit.io.isBType <= controlUnit.io.isBType @[PiplineCPUwithBPandF.scala 223:29]
+    aluControlUnit.io.isIType <= controlUnit.io.isIType @[PiplineCPUwithBPandF.scala 224:29]
+    aluControlUnit.io.isRType <= controlUnit.io.isRType @[PiplineCPUwithBPandF.scala 225:29]
+    aluControlUnit.io.isWord <= controlUnit.io.isWord @[PiplineCPUwithBPandF.scala 226:28]
+    aluControlUnit.io.funct3 <= funct3 @[PiplineCPUwithBPandF.scala 227:28]
+    aluControlUnit.io.funct7 <= funct7 @[PiplineCPUwithBPandF.scala 228:28]
+    regUnit.io.writeEnable <= memWBStageRegs.io.out.writeEnable @[PiplineCPUwithBPandF.scala 230:26]
+    regUnit.io.rs1 <= rs1 @[PiplineCPUwithBPandF.scala 231:18]
+    regUnit.io.rs2 <= rs2 @[PiplineCPUwithBPandF.scala 232:18]
+    regUnit.io.rd <= wbRd @[PiplineCPUwithBPandF.scala 233:17]
+    regUnit.io.writeData <= resSelectUnit.io.out @[PiplineCPUwithBPandF.scala 234:24]
+    inst2ImmUnit.io.inst <= ifIDStageRegs.io.out.inst @[PiplineCPUwithBPandF.scala 236:24]
+    node _pcSelectUnit_io_pcPlus4_T = add(idEXEStageRegs.io.out.pc, UInt<3>("h4")) @[PiplineCPUwithBPandF.scala 238:36]
+    node _pcSelectUnit_io_pcPlus4_T_1 = tail(_pcSelectUnit_io_pcPlus4_T, 1) @[PiplineCPUwithBPandF.scala 238:36]
+    pcSelectUnit.io.pcPlus4 <= _pcSelectUnit_io_pcPlus4_T_1 @[PiplineCPUwithBPandF.scala 238:27]
+    node _pcSelectUnit_io_pcPlusImm_T = add(idEXEStageRegs.io.out.pc, idEXEStageRegs.io.out.imm) @[PiplineCPUwithBPandF.scala 239:38]
+    node _pcSelectUnit_io_pcPlusImm_T_1 = tail(_pcSelectUnit_io_pcPlusImm_T, 1) @[PiplineCPUwithBPandF.scala 239:38]
+    pcSelectUnit.io.pcPlusImm <= _pcSelectUnit_io_pcPlusImm_T_1 @[PiplineCPUwithBPandF.scala 239:29]
+    pcSelectUnit.io.isJALR <= idEXEStageRegs.io.out.isJALR @[PiplineCPUwithBPandF.scala 240:26]
+    pcSelectUnit.io.isBType <= idEXEStageRegs.io.out.isBType @[PiplineCPUwithBPandF.scala 241:27]
+    pcSelectUnit.io.isJump <= idEXEStageRegs.io.out.isJump @[PiplineCPUwithBPandF.scala 242:26]
+    node _pcSelectUnit_io_isTrue_T = bits(alu.io.result, 0, 0) @[PiplineCPUwithBPandF.scala 243:42]
+    pcSelectUnit.io.isTrue <= _pcSelectUnit_io_isTrue_T @[PiplineCPUwithBPandF.scala 243:26]
+    pcSelectUnit.io.aluResult <= alu.io.result @[PiplineCPUwithBPandF.scala 244:29]
+    alu.io.aluOperation <= idEXEStageRegs.io.out.aluOperation @[PiplineCPUwithBPandF.scala 246:23]
+    alu.io.x <= idEXEStageRegs.io.out.aluX @[PiplineCPUwithBPandF.scala 247:12]
+    alu.io.y <= idEXEStageRegs.io.out.aluY @[PiplineCPUwithBPandF.scala 248:12]
+    dataMemory.io.memRead <= exeMEMStageRegs.io.out.memRead @[PiplineCPUwithBPandF.scala 250:25]
+    dataMemory.io.memWrite <= exeMEMStageRegs.io.out.memWrite @[PiplineCPUwithBPandF.scala 251:26]
+    dataMemory.io.address <= exeMEMStageRegs.io.out.aluResult @[PiplineCPUwithBPandF.scala 252:25]
+    dataMemory.io.writeData <= exeMEMStageRegs.io.out.readDataRs2 @[PiplineCPUwithBPandF.scala 253:27]
+    dataMemory.io.bitType <= bitType @[PiplineCPUwithBPandF.scala 254:25]
+    dataMemory.io.isUnsigned <= isUnsigned @[PiplineCPUwithBPandF.scala 255:28]
+    resSelectUnit.io.isJump <= memWBStageRegs.io.out.isJump @[PiplineCPUwithBPandF.scala 257:27]
+    resSelectUnit.io.immALUToReg <= memWBStageRegs.io.out.immALUToReg @[PiplineCPUwithBPandF.scala 258:32]
+    resSelectUnit.io.memRead <= memWBStageRegs.io.out.memRead @[PiplineCPUwithBPandF.scala 259:28]
+    resSelectUnit.io.readData <= memWBStageRegs.io.out.readData @[PiplineCPUwithBPandF.scala 260:29]
+    resSelectUnit.io.aluResult <= memWBStageRegs.io.out.aluResult @[PiplineCPUwithBPandF.scala 261:30]
+    resSelectUnit.io.imm <= memWBStageRegs.io.out.imm @[PiplineCPUwithBPandF.scala 262:24]
+    node _resSelectUnit_io_pcPlus4_T = add(memWBStageRegs.io.out.pc, UInt<3>("h4")) @[PiplineCPUwithBPandF.scala 263:36]
+    node _resSelectUnit_io_pcPlus4_T_1 = tail(_resSelectUnit_io_pcPlus4_T, 1) @[PiplineCPUwithBPandF.scala 263:36]
+    resSelectUnit.io.pcPlus4 <= _resSelectUnit_io_pcPlus4_T_1 @[PiplineCPUwithBPandF.scala 263:28]
 

src/main/scala/CPU/PiplineCPU/PiplineCPUwithBPandF.scala

@@ -188,9 +188,6 @@ class PiplineCPUwithBPandF(
   branchPredictor.io.selectPC := pcSelectUnit.io.nextPC
   branchPredictor.io.jump := pcSelectUnit.io.jump
 
-  dataForwardingUnit.io.inWriteEnable := memWBStageRegs.io.out.writeEnable
-  dataForwardingUnit.io.inRd := wbRd
-  dataForwardingUnit.io.inData := resSelectUnit.io.out
   dataForwardingUnit.io.pcRs1ToAlu := controlUnit.io.pcRs1ToALU
   dataForwardingUnit.io.rs1 := rs1
   dataForwardingUnit.io.memWrite := controlUnit.io.memWrite
@@ -230,11 +227,11 @@ class PiplineCPUwithBPandF(
   aluControlUnit.io.funct3 := funct3
   aluControlUnit.io.funct7 := funct7
 
-  regUnit.io.writeEnable := dataForwardingUnit.io.writeEnable
+  regUnit.io.writeEnable := memWBStageRegs.io.out.writeEnable
   regUnit.io.rs1 := rs1
   regUnit.io.rs2 := rs2
-  regUnit.io.rd := dataForwardingUnit.io.rd
-  regUnit.io.writeData := dataForwardingUnit.io.data
+  regUnit.io.rd := wbRd
+  regUnit.io.writeData := resSelectUnit.io.out
 
   inst2ImmUnit.io.inst := idInst
 

src/main/scala/CPU/PiplineCPU/PiplineCPUwithForwarding.scala

@@ -185,9 +185,6 @@ class PiplineCPUwithForwarding(
   branchControlUnit.io.exePC := exePC
   branchControlUnit.io.selectPC := pcSelectUnit.io.nextPC
 
-  dataForwardingUnit.io.inWriteEnable := memWBStageRegs.io.out.writeEnable
-  dataForwardingUnit.io.inRd := wbRd
-  dataForwardingUnit.io.inData := resSelectUnit.io.out
   dataForwardingUnit.io.pcRs1ToAlu := controlUnit.io.pcRs1ToALU
   dataForwardingUnit.io.rs1 := rs1
   dataForwardingUnit.io.memWrite := controlUnit.io.memWrite
@@ -227,11 +224,11 @@ class PiplineCPUwithForwarding(
   aluControlUnit.io.funct3 := funct3
   aluControlUnit.io.funct7 := funct7
 
-  regUnit.io.writeEnable := dataForwardingUnit.io.writeEnable
+  regUnit.io.writeEnable := memWBStageRegs.io.out.writeEnable
   regUnit.io.rs1 := rs1
   regUnit.io.rs2 := rs2
-  regUnit.io.rd := dataForwardingUnit.io.rd
-  regUnit.io.writeData := dataForwardingUnit.io.data
+  regUnit.io.rd := wbRd
+  regUnit.io.writeData := resSelectUnit.io.out
 
   inst2ImmUnit.io.inst := idInst
 

src/main/scala/CPU/PiplineComponts/DataForwardingUnit.scala

@@ -6,21 +6,17 @@ import CPU.CPUConfig._
 import CPU._
 
 /**
- * <b>[[数据旁路转发器]]</b>
+ * <b>[[数据冒险判断器]]</b>
  * <p>
- * 用旁路转发的方式解决流水线 CPU 的数据冒险问题。
+ * 用组合电路判断是否存在数据冒险, 将判断的逻辑从旁路转发器中提取出来, 符合模块化设计
  * <p>
  * [[input]]
  * <p>
  * [[output]]
  */
-class DataForwardingUnit extends Module {
+class HazardJudgement extends Module {
   val io = IO(new Bundle {
     /* input */
-    val inWriteEnable = Input(Bool())
-    val inRd = Input(UInt(5.W))
-    val inData = Input(UInt(XLEN.W))
-
     val pcRs1ToAlu = Input(Bool())
     val rs1 = Input(UInt(5.W))
 
@@ -33,6 +29,58 @@ class DataForwardingUnit extends Module {
 
     val memWriteEnable = Input(Bool())
     val memRd = Input(UInt(5.W))
+    /* output */
+    val ifRS1EXE = Output(Bool())
+    val ifRS2EXE = Output(Bool())
+    val ifRS1MEM = Output(Bool())
+    val ifRS2MEM = Output(Bool())
+  })
+  // 默认为寄存器 zero
+  val useRs1 = WireDefault(0.U(5.W)) // 将读出的寄存器 rs1
+  val useRs2 = WireDefault(0.U(5.W)) // 将读出的寄存器 rs2
+  val exeWriteRd = WireDefault(0.U(5.W)) // exe 会写入的寄存器
+  val memWriteRd = WireDefault(0.U(5.W)) // mem 会写入的寄存器
+
+  /* 组合电路生成对应的寄存器, 简化状态机的判断 */
+  when(io.pcRs1ToAlu === false.B) { useRs1 := io.rs1 }
+  when(io.immRs2ToAlu === false.B || io.memWrite === true.B) {
+    useRs2 := io.rs2
+  }
+  when(io.exeWriteEnable === true.B) { exeWriteRd := io.exeRd }
+  when(io.memWriteEnable === true.B) { memWriteRd := io.memRd }
+
+  val ifRS1EXE =
+    (exeWriteRd =/= 0.U) && (useRs1 === exeWriteRd) // EXE 阶段和 rs1 数据冲突
+  val ifRS2EXE =
+    (exeWriteRd =/= 0.U) && (useRs2 === exeWriteRd) // EXE 阶段和 rs2 数据冲突
+
+  val ifRS1MEM =
+    (memWriteRd =/= 0.U) && (useRs1 === memWriteRd) // MEM 阶段和 rs1 数据冲突
+  val ifRS2MEM =
+    (memWriteRd =/= 0.U) && (useRs2 === memWriteRd) // MEM 阶段和 rs1 数据冲突
+
+  io.ifRS1EXE := ifRS1EXE
+  io.ifRS2EXE := ifRS2EXE
+  io.ifRS1MEM := ifRS1MEM
+  io.ifRS2MEM := ifRS2MEM
+}
+
+/**
+ * <b>[[数据转发器]]</b>
+ * <p>
+ * 旁路转发中的数据转发模块
+ * <p>
+ * [[input]]
+ * <p>
+ * [[output]]
+ */
+class DataForwarding extends Module {
+  val io = IO(new Bundle {
+    /* input */
+    val ifRS1EXE = Input(Bool())
+    val ifRS2EXE = Input(Bool())
+    val ifRS1MEM = Input(Bool())
+    val ifRS2MEM = Input(Bool())
 
     val exeIsJump = Input(Bool())
     val exeImmALUToReg = Input(Bool())
@@ -51,10 +99,6 @@ class DataForwardingUnit extends Module {
     val memPC = Input(UInt(XLEN.W)) // MEM 阶段的 PC
 
     /* output */
-    val writeEnable = Output(Bool())
-    val rd = Output(UInt(5.W))
-    val data = Output(UInt(XLEN.W))
-
     val keep = Output(Bool()) // 控制 BranchControlUnit
     val stall = Output(Bool()) // 连 IF/ID 的寄存器组
     val flush = Output(Bool()) // 连 ID/EXE 的寄存器组
@@ -86,30 +130,6 @@ class DataForwardingUnit extends Module {
   val forwardData1 = WireDefault(0.U(XLEN.W))
   val forwardData2 = WireDefault(0.U(XLEN.W))
 
-  // 默认为寄存器 zero
-  val useRs1 = WireDefault(0.U(5.W)) // 将读出的寄存器 rs1
-  val useRs2 = WireDefault(0.U(5.W)) // 将读出的寄存器 rs2
-  val exeWriteRd = WireDefault(0.U(5.W)) // exe 会写入的寄存器
-  val memWriteRd = WireDefault(0.U(5.W)) // mem 会写入的寄存器
-
-  /* 组合电路生成对应的寄存器, 简化状态机的判断 */
-  when(io.pcRs1ToAlu === false.B) { useRs1 := io.rs1 }
-  when(io.immRs2ToAlu === false.B || io.memWrite === true.B) {
-    useRs2 := io.rs2
-  }
-  when(io.exeWriteEnable === true.B) { exeWriteRd := io.exeRd }
-  when(io.memWriteEnable === true.B) { memWriteRd := io.memRd }
-
-  val ifRS1EXE =
-    (exeWriteRd =/= 0.U) && (useRs1 === exeWriteRd) // EXE 阶段和 rs1 数据冲突
-  val ifRS2EXE =
-    (exeWriteRd =/= 0.U) && (useRs2 === exeWriteRd) // EXE 阶段和 rs2 数据冲突
-
-  val ifRS1MEM =
-    (memWriteRd =/= 0.U) && (useRs1 === memWriteRd) // MEM 阶段和 rs1 数据冲突
-  val ifRS2MEM =
-    (memWriteRd =/= 0.U) && (useRs2 === memWriteRd) // MEM 阶段和 rs1 数据冲突
-
   val exeResWire = WireDefault(io.exeALUResult)
   when(io.exeIsJump === true.B) {
     exeResWire := io.exePC + 4.U
@@ -135,7 +155,7 @@ class DataForwardingUnit extends Module {
       ifNeedRs1 := false.B
       ifNeedRs2 := false.B
 
-      when(ifRS1EXE === true.B) {
+      when(io.ifRS1EXE === true.B) {
         when(io.exeMemRead === true.B) { // 得等到 MEM 阶段才能得到数据
           ifNeedRs1 := true.B // 记录 rs1 需要转发
           pcRecordReg := io.exePC // 记录数据源 PC
@@ -148,13 +168,13 @@ class DataForwardingUnit extends Module {
           forwardRs1 := true.B // 表示将数据转发到 rs1
         }
       }.otherwise { // EXE 阶段比 MEM 阶段优先级更高
-        when(ifRS1MEM === true.B) {
+        when(io.ifRS1MEM === true.B) {
           forwardData1 := memResWire
           forwardRs1 := true.B // 表示将数据转发到 rs1
         }
       }
 
-      when(ifRS2EXE === true.B) {
+      when(io.ifRS2EXE === true.B) {
         when(io.exeMemRead === true.B) { // 得等到 MEM 阶段才能得到数据
           ifNeedRs2 := true.B // 记录 rs2 需要转发
           pcRecordReg := io.exePC // 记录数据源 PC
@@ -167,7 +187,7 @@ class DataForwardingUnit extends Module {
           forwardRs2 := true.B // 表示将数据转发到 rs2
         }
       }.otherwise { // EXE 阶段比 MEM 阶段优先级更高
-        when(ifRS2MEM === true.B) {
+        when(io.ifRS2MEM === true.B) {
           forwardData2 := memResWire
           forwardRs2 := true.B // 表示将数据转发到 rs1
         }
@@ -205,22 +225,114 @@ class DataForwardingUnit extends Module {
   io.forwardRs2 := forwardRs2
   io.forwardData1 := forwardData1
   io.forwardData2 := forwardData2
+}
+
+/**
+ * <b>[[数据旁路转发组]]</b>
+ * <p>
+ * 用旁路转发的方式解决流水线 CPU 的数据冒险问题。
+ * 分为 数据冒险判断器 和 数据转发器 两个模块。
+ * <p>
+ * [[input]]
+ * <p>
+ * [[output]]
+ */
+class DataForwardingUnit extends Module {
+  val io = IO(new Bundle {
+    /* input */
+    val pcRs1ToAlu = Input(Bool())
+    val rs1 = Input(UInt(5.W))
+
+    val memWrite = Input(Bool()) // 内存写入也会用到 rs2
+    val immRs2ToAlu = Input(Bool())
+    val rs2 = Input(UInt(5.W))
+
+    val exeWriteEnable = Input(Bool())
+    val exeRd = Input(UInt(5.W))
+
+    val memWriteEnable = Input(Bool())
+    val memRd = Input(UInt(5.W))
+
+    val exeIsJump = Input(Bool())
+    val exeImmALUToReg = Input(Bool())
+    val exeMemRead = Input(Bool())
+    val exeALUResult = Input(UInt(XLEN.W))
+    val exeImm = Input(UInt(XLEN.W))
+
+    val memIsJump = Input(Bool())
+    val memImmALUToReg = Input(Bool())
+    val memMemRead = Input(Bool())
+    val memReadData = Input(UInt(XLEN.W))
+    val memALUResult = Input(UInt(XLEN.W))
+    val memImm = Input(UInt(XLEN.W))
+
+    val exePC = Input(UInt(XLEN.W)) // EXE 阶段的 PC
+    val memPC = Input(UInt(XLEN.W)) // MEM 阶段的 PC
 
-  // 这三个保持不变
-  io.writeEnable := io.inWriteEnable
-  io.rd := io.inRd
-  io.data := io.inData
+    /* output */
+    val keep = Output(Bool()) // 控制 BranchControlUnit
+    val stall = Output(Bool()) // 连 IF/ID 的寄存器组
+    val flush = Output(Bool()) // 连 ID/EXE 的寄存器组
+
+    val forwardRs1 = Output(Bool()) // 是否将输出转发到 rs1
+    val forwardRs2 = Output(Bool()) // 是否将输出转发到 rs2
+    val forwardData1 = Output(UInt(XLEN.W)) // 转发到 rs1 的输出
+    val forwardData2 = Output(UInt(XLEN.W)) // 转发到 rs2 的输出
+  })
+
+  val hazardJudgement = Module(new HazardJudgement())
+  val dataForwarding = Module(new DataForwarding())
+
+  hazardJudgement.io.pcRs1ToAlu := io.pcRs1ToAlu
+  hazardJudgement.io.rs1 := io.rs1
+  hazardJudgement.io.memWrite := io.memWrite
+  hazardJudgement.io.immRs2ToAlu := io.immRs2ToAlu
+  hazardJudgement.io.rs2 := io.rs2
+  hazardJudgement.io.exeWriteEnable := io.exeWriteEnable
+  hazardJudgement.io.exeRd := io.exeRd
+  hazardJudgement.io.memWriteEnable := io.memWriteEnable
+  hazardJudgement.io.memRd := io.memRd
+
+  dataForwarding.io.ifRS1EXE := hazardJudgement.io.ifRS1EXE
+  dataForwarding.io.ifRS2EXE := hazardJudgement.io.ifRS2EXE
+  dataForwarding.io.ifRS1MEM := hazardJudgement.io.ifRS1MEM
+  dataForwarding.io.ifRS2MEM := hazardJudgement.io.ifRS2MEM
+
+  dataForwarding.io.exeIsJump := io.exeIsJump
+  dataForwarding.io.exeImmALUToReg := io.exeImmALUToReg
+  dataForwarding.io.exeMemRead := io.exeMemRead
+  dataForwarding.io.exeALUResult := io.exeALUResult
+  dataForwarding.io.exeImm := io.exeImm
+
+  dataForwarding.io.memIsJump := io.memIsJump
+  dataForwarding.io.memImmALUToReg := io.memImmALUToReg
+  dataForwarding.io.memMemRead := io.memMemRead
+  dataForwarding.io.memReadData := io.memReadData
+  dataForwarding.io.memALUResult := io.memALUResult
+  dataForwarding.io.memImm := io.memImm
+
+  dataForwarding.io.exePC := io.exePC
+  dataForwarding.io.memPC := io.memPC
+
+  io.keep := dataForwarding.io.keep
+  io.stall := dataForwarding.io.stall
+  io.flush := dataForwarding.io.flush
+
+  io.forwardRs1 := dataForwarding.io.forwardRs1
+  io.forwardRs2 := dataForwarding.io.forwardRs2
+  io.forwardData1 := dataForwarding.io.forwardData1
+  io.forwardData2 := dataForwarding.io.forwardData2
 
   // **************** print **************** //
   val needBinary = List[Data]()
   val needDec =
-    List[Data](io.inData, io.rs1, io.rs2, io.exeRd, io.memRd, io.data)
-  val needHex = List[Data](io.exePC, io.memPC, pcRecordReg)
+    List[Data](io.rs1, io.rs2, io.exeRd, io.memRd)
+  val needHex = List[Data](io.exePC, io.memPC)
   val needBool = List[Bool]()
     .appendedAll(io.getElements.filter(data => data.isInstanceOf[Bool]))
 
   val needDelete = List[Data]()
-  val needAdd = List[Data](stateReg, pcRecordReg)
+  val needAdd = List[Data]()
 
   if (DebugControl.DataControlUnitIOPrint) {
     CPUPrintf.printfIO(
@@ -237,3 +349,11 @@ class DataForwardingUnit extends Module {
     )
   }
 }
+
+object DataForwardingUnit {
+  def main(args: Array[String]) = {
+    print(getVerilogString(new DataForwardingUnit()))
+
+    print("\n[Success]\n")
+  }
+}

src/test/scala/CPU/CPUTester/PiplineCPUTester.scala

@@ -26,7 +26,7 @@ trait TestFuncPiplineCPU {
 
   /* 控制信号 */
   val printToFile = true // 是否打印到文件
-  val timeOut = 2000 // 超时, 以周期为单位, 0 表示无限制
+  val timeOut = 3000 // 超时, 以周期为单位, 0 表示无限制
   val begin = 0 // 开始完全输出的起始周期
   val end = 0 // 结束完全输出的结束周期, 0 表示不会结束
   val printInstPC = true // 是否由 Tester 打印指令和 PC
@@ -231,10 +231,10 @@ class PiplineCPUTester
     with ChiselScalatestTester
     with TestcaseSet
     with TestFuncPiplineCPU {
-
-  "CPU" should "pass" in {
-    // sbt "testOnly CPU.CPUTester.PiplineCPUTester" > src/test/hex/fibonacci/pipline_stage.log
-
+  def testPiplineCPUGeneral(
+      ifHasBranchPredictor: Boolean, // 是否有分支预测
+      ifHasForwarding: Boolean // 是否有旁路转发
+  ) = {
     for (testcasePair <- testcases) {
       val dir = s"${System
           .getProperty("user.dir")}/${testcasePair._1}"
@@ -275,9 +275,6 @@ class PiplineCPUTester
       var myPrint: Any => Unit = print
       var outFile: PrintWriter = null
 
-      val ifHasBranchPredictor = true // 是否有分支预测
-      val ifHasForwarding = true // 是否有旁路转发
-
       if (printToFile) {
         val filePath =
           if (ifHasBranchPredictor)
@@ -317,4 +314,19 @@ class PiplineCPUTester
       }
     }
   }
+
+  // 记录 sbt 指令
+  // sbt "testOnly CPU.CPUTester.PiplineCPUTester" > src/test/hex/fibonacci/pipline_stage.log
+
+  "Base CPU" should "pass" in {
+    testPiplineCPUGeneral(false, false) // 无分支预测, 无旁路转发
+  }
+
+  "CPU with ByPass Forwarding" should "pass" in {
+    testPiplineCPUGeneral(false, true) // 无分支预测, 有旁路转发
+  }
+
+  "CPU with BF and F" should "pass" in {
+    testPiplineCPUGeneral(true, true) // 有分支预测, 有旁路转发
+  }
 }

src/test/scala/CPU/CPUTester/SingleCycleCPUTester.scala

@@ -258,7 +258,11 @@ class SingleCycleCPUTester
 }
 
 trait TestcaseSet { // 测试集
-  val testcases = List(
+  val testcasesTest = List(
+    /* dir, fileName, startAddress */
+    ("src/test/hex/myTest", "myTest", 0x0)
+  )
+  val testcasesBase = List(
     /* dir, fileName, startAddress */
 
     ("src/test/hex/fibonacci_recursion", "fibonacci_recursion", 0x98), // 耗时比较长
@@ -393,4 +397,8 @@ trait TestcaseSet { // 测试集
     // ("src/test/hex/dino/target/csrrsi", "csrrsi", 0x0),
     // ("src/test/hex/dino/target/mret", "mret", 0x0),
   )
+
+  val ifAllTest = true // 是否全部测试
+
+  val testcases = if (ifAllTest) testcasesBase else testcasesTest
 }