流水线草稿版完成

generated/PiplineCPU/PiplineCPU.anno.json

+[
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"generated/PiplineCPU"
+  }
+]
\ No newline at end of file

generated/SingleCycleCPU.anno.json → generated/SingleCycleCPU/SingleCycleCPU.anno.json

@@ -17,6 +17,6 @@
   },
   {
     "class":"firrtl.transforms.BlackBoxTargetDirAnno",
-    "targetDir":"generated"
+    "targetDir":"generated/SingleCycleCPU"
   }
 ]
\ No newline at end of file

generated/SingleCycleCPU.fir → generated/SingleCycleCPU/SingleCycleCPU.fir

@@ -402,43 +402,43 @@ circuit SingleCycleCPU :
     node _io_readDataRs2_T = eq(io.rs2, UInt<1>("h0")) @[RegUnit.scala 51:32]
     node _io_readDataRs2_T_1 = mux(_io_readDataRs2_T, UInt<1>("h0"), regGroup[io.rs2]) @[RegUnit.scala 51:24]
     io.readDataRs2 <= _io_readDataRs2_T_1 @[RegUnit.scala 51:18]
-    node _T = eq(io.writeEnable, UInt<1>("h1")) @[RegUnit.scala 67:23]
-    node _T_1 = neq(io.rd, UInt<1>("h0")) @[RegUnit.scala 67:43]
-    node _T_2 = and(_T, _T_1) @[RegUnit.scala 67:34]
-    when _T_2 : @[RegUnit.scala 67:52]
-      regGroup[io.rd] <= io.writeData @[RegUnit.scala 68:21]
-    io.regAll[0] <= UInt<1>("h0") @[RegUnit.scala 71:16]
-    io.regAll[1] <= regGroup[1] @[RegUnit.scala 73:18]
-    io.regAll[2] <= regGroup[2] @[RegUnit.scala 73:18]
-    io.regAll[3] <= regGroup[3] @[RegUnit.scala 73:18]
-    io.regAll[4] <= regGroup[4] @[RegUnit.scala 73:18]
-    io.regAll[5] <= regGroup[5] @[RegUnit.scala 73:18]
-    io.regAll[6] <= regGroup[6] @[RegUnit.scala 73:18]
-    io.regAll[7] <= regGroup[7] @[RegUnit.scala 73:18]
-    io.regAll[8] <= regGroup[8] @[RegUnit.scala 73:18]
-    io.regAll[9] <= regGroup[9] @[RegUnit.scala 73:18]
-    io.regAll[10] <= regGroup[10] @[RegUnit.scala 73:18]
-    io.regAll[11] <= regGroup[11] @[RegUnit.scala 73:18]
-    io.regAll[12] <= regGroup[12] @[RegUnit.scala 73:18]
-    io.regAll[13] <= regGroup[13] @[RegUnit.scala 73:18]
-    io.regAll[14] <= regGroup[14] @[RegUnit.scala 73:18]
-    io.regAll[15] <= regGroup[15] @[RegUnit.scala 73:18]
-    io.regAll[16] <= regGroup[16] @[RegUnit.scala 73:18]
-    io.regAll[17] <= regGroup[17] @[RegUnit.scala 73:18]
-    io.regAll[18] <= regGroup[18] @[RegUnit.scala 73:18]
-    io.regAll[19] <= regGroup[19] @[RegUnit.scala 73:18]
-    io.regAll[20] <= regGroup[20] @[RegUnit.scala 73:18]
-    io.regAll[21] <= regGroup[21] @[RegUnit.scala 73:18]
-    io.regAll[22] <= regGroup[22] @[RegUnit.scala 73:18]
-    io.regAll[23] <= regGroup[23] @[RegUnit.scala 73:18]
-    io.regAll[24] <= regGroup[24] @[RegUnit.scala 73:18]
-    io.regAll[25] <= regGroup[25] @[RegUnit.scala 73:18]
-    io.regAll[26] <= regGroup[26] @[RegUnit.scala 73:18]
-    io.regAll[27] <= regGroup[27] @[RegUnit.scala 73:18]
-    io.regAll[28] <= regGroup[28] @[RegUnit.scala 73:18]
-    io.regAll[29] <= regGroup[29] @[RegUnit.scala 73:18]
-    io.regAll[30] <= regGroup[30] @[RegUnit.scala 73:18]
-    io.regAll[31] <= regGroup[31] @[RegUnit.scala 73:18]
+    node _T = eq(io.writeEnable, UInt<1>("h1")) @[RegUnit.scala 70:23]
+    node _T_1 = neq(io.rd, UInt<1>("h0")) @[RegUnit.scala 70:43]
+    node _T_2 = and(_T, _T_1) @[RegUnit.scala 70:34]
+    when _T_2 : @[RegUnit.scala 70:52]
+      regGroup[io.rd] <= io.writeData @[RegUnit.scala 71:21]
+    io.regAll[0] <= UInt<1>("h0") @[RegUnit.scala 74:16]
+    io.regAll[1] <= regGroup[1] @[RegUnit.scala 76:18]
+    io.regAll[2] <= regGroup[2] @[RegUnit.scala 76:18]
+    io.regAll[3] <= regGroup[3] @[RegUnit.scala 76:18]
+    io.regAll[4] <= regGroup[4] @[RegUnit.scala 76:18]
+    io.regAll[5] <= regGroup[5] @[RegUnit.scala 76:18]
+    io.regAll[6] <= regGroup[6] @[RegUnit.scala 76:18]
+    io.regAll[7] <= regGroup[7] @[RegUnit.scala 76:18]
+    io.regAll[8] <= regGroup[8] @[RegUnit.scala 76:18]
+    io.regAll[9] <= regGroup[9] @[RegUnit.scala 76:18]
+    io.regAll[10] <= regGroup[10] @[RegUnit.scala 76:18]
+    io.regAll[11] <= regGroup[11] @[RegUnit.scala 76:18]
+    io.regAll[12] <= regGroup[12] @[RegUnit.scala 76:18]
+    io.regAll[13] <= regGroup[13] @[RegUnit.scala 76:18]
+    io.regAll[14] <= regGroup[14] @[RegUnit.scala 76:18]
+    io.regAll[15] <= regGroup[15] @[RegUnit.scala 76:18]
+    io.regAll[16] <= regGroup[16] @[RegUnit.scala 76:18]
+    io.regAll[17] <= regGroup[17] @[RegUnit.scala 76:18]
+    io.regAll[18] <= regGroup[18] @[RegUnit.scala 76:18]
+    io.regAll[19] <= regGroup[19] @[RegUnit.scala 76:18]
+    io.regAll[20] <= regGroup[20] @[RegUnit.scala 76:18]
+    io.regAll[21] <= regGroup[21] @[RegUnit.scala 76:18]
+    io.regAll[22] <= regGroup[22] @[RegUnit.scala 76:18]
+    io.regAll[23] <= regGroup[23] @[RegUnit.scala 76:18]
+    io.regAll[24] <= regGroup[24] @[RegUnit.scala 76:18]
+    io.regAll[25] <= regGroup[25] @[RegUnit.scala 76:18]
+    io.regAll[26] <= regGroup[26] @[RegUnit.scala 76:18]
+    io.regAll[27] <= regGroup[27] @[RegUnit.scala 76:18]
+    io.regAll[28] <= regGroup[28] @[RegUnit.scala 76:18]
+    io.regAll[29] <= regGroup[29] @[RegUnit.scala 76:18]
+    io.regAll[30] <= regGroup[30] @[RegUnit.scala 76:18]
+    io.regAll[31] <= regGroup[31] @[RegUnit.scala 76:18]
     node needAdd_0 = cat(UInt<1>("h0"), io.rs1) @[Cat.scala 33:92]
     node needAdd_1 = cat(UInt<1>("h0"), io.rs2) @[Cat.scala 33:92]
     node needAdd_2 = cat(UInt<1>("h0"), io.rd) @[Cat.scala 33:92]
@@ -551,10 +551,10 @@ circuit SingleCycleCPU :
         when _T_8 : @[ALU.scala 81:33]
           node _resWire_T_11 = add(x32, y32) @[ALU.scala 82:43]
           node _resWire_T_12 = tail(_resWire_T_11, 1) @[ALU.scala 82:43]
-          node resWire_sign = bits(_resWire_T_12, 31, 31) @[CPUUtils.scala 114:33]
+          node resWire_sign = bits(_resWire_T_12, 31, 31) @[CPUUtils.scala 117:33]
           node _resWire_T_13 = bits(resWire_sign, 0, 0) @[Bitwise.scala 77:15]
           node _resWire_T_14 = mux(_resWire_T_13, UInt<32>("hffffffff"), UInt<32>("h0")) @[Bitwise.scala 77:12]
-          node _resWire_T_15 = bits(_resWire_T_12, 31, 0) @[CPUUtils.scala 115:36]
+          node _resWire_T_15 = bits(_resWire_T_12, 31, 0) @[CPUUtils.scala 118:36]
           node _resWire_T_16 = cat(_resWire_T_14, _resWire_T_15) @[Cat.scala 33:92]
           resWire <= _resWire_T_16 @[ALU.scala 82:19]
         else :
@@ -568,10 +568,10 @@ circuit SingleCycleCPU :
           when _T_10 : @[ALU.scala 89:33]
             node _resWire_T_19 = sub(x32, y32) @[ALU.scala 90:43]
             node _resWire_T_20 = tail(_resWire_T_19, 1) @[ALU.scala 90:43]
-            node resWire_sign_1 = bits(_resWire_T_20, 31, 31) @[CPUUtils.scala 114:33]
+            node resWire_sign_1 = bits(_resWire_T_20, 31, 31) @[CPUUtils.scala 117:33]
             node _resWire_T_21 = bits(resWire_sign_1, 0, 0) @[Bitwise.scala 77:15]
             node _resWire_T_22 = mux(_resWire_T_21, UInt<32>("hffffffff"), UInt<32>("h0")) @[Bitwise.scala 77:12]
-            node _resWire_T_23 = bits(_resWire_T_20, 31, 0) @[CPUUtils.scala 115:36]
+            node _resWire_T_23 = bits(_resWire_T_20, 31, 0) @[CPUUtils.scala 118:36]
             node _resWire_T_24 = cat(_resWire_T_22, _resWire_T_23) @[Cat.scala 33:92]
             resWire <= _resWire_T_24 @[ALU.scala 90:19]
           else :
@@ -584,10 +584,10 @@ circuit SingleCycleCPU :
             node _T_12 = eq(isWord, UInt<1>("h1")) @[ALU.scala 97:21]
             when _T_12 : @[ALU.scala 97:33]
               node _resWire_T_27 = dshl(x32, shamtW) @[ALU.scala 98:43]
-              node resWire_sign_2 = bits(_resWire_T_27, 31, 31) @[CPUUtils.scala 114:33]
+              node resWire_sign_2 = bits(_resWire_T_27, 31, 31) @[CPUUtils.scala 117:33]
               node _resWire_T_28 = bits(resWire_sign_2, 0, 0) @[Bitwise.scala 77:15]
               node _resWire_T_29 = mux(_resWire_T_28, UInt<32>("hffffffff"), UInt<32>("h0")) @[Bitwise.scala 77:12]
-              node _resWire_T_30 = bits(_resWire_T_27, 31, 0) @[CPUUtils.scala 115:36]
+              node _resWire_T_30 = bits(_resWire_T_27, 31, 0) @[CPUUtils.scala 118:36]
               node _resWire_T_31 = cat(_resWire_T_29, _resWire_T_30) @[Cat.scala 33:92]
               resWire <= _resWire_T_31 @[ALU.scala 98:19]
             else :
@@ -616,10 +616,10 @@ circuit SingleCycleCPU :
                     node _T_17 = eq(isWord, UInt<1>("h1")) @[ALU.scala 117:21]
                     when _T_17 : @[ALU.scala 117:33]
                       node _resWire_T_38 = dshr(x32, shamtW) @[ALU.scala 118:43]
-                      node resWire_sign_3 = bits(_resWire_T_38, 31, 31) @[CPUUtils.scala 114:33]
+                      node resWire_sign_3 = bits(_resWire_T_38, 31, 31) @[CPUUtils.scala 117:33]
                       node _resWire_T_39 = bits(resWire_sign_3, 0, 0) @[Bitwise.scala 77:15]
                       node _resWire_T_40 = mux(_resWire_T_39, UInt<32>("hffffffff"), UInt<32>("h0")) @[Bitwise.scala 77:12]
-                      node _resWire_T_41 = bits(_resWire_T_38, 31, 0) @[CPUUtils.scala 115:36]
+                      node _resWire_T_41 = bits(_resWire_T_38, 31, 0) @[CPUUtils.scala 118:36]
                       node _resWire_T_42 = cat(_resWire_T_40, _resWire_T_41) @[Cat.scala 33:92]
                       resWire <= _resWire_T_42 @[ALU.scala 118:19]
                     else :
@@ -633,10 +633,10 @@ circuit SingleCycleCPU :
                         node _resWire_T_44 = asSInt(x32) @[ALU.scala 127:18]
                         node _resWire_T_45 = dshr(_resWire_T_44, shamtW) @[ALU.scala 127:25]
                         node _resWire_T_46 = asUInt(_resWire_T_45) @[ALU.scala 127:36]
-                        node resWire_sign_4 = bits(_resWire_T_46, 31, 31) @[CPUUtils.scala 114:33]
+                        node resWire_sign_4 = bits(_resWire_T_46, 31, 31) @[CPUUtils.scala 117:33]
                         node _resWire_T_47 = bits(resWire_sign_4, 0, 0) @[Bitwise.scala 77:15]
                         node _resWire_T_48 = mux(_resWire_T_47, UInt<32>("hffffffff"), UInt<32>("h0")) @[Bitwise.scala 77:12]
-                        node _resWire_T_49 = bits(_resWire_T_46, 31, 0) @[CPUUtils.scala 115:36]
+                        node _resWire_T_49 = bits(_resWire_T_46, 31, 0) @[CPUUtils.scala 118:36]
                         node _resWire_T_50 = cat(_resWire_T_48, _resWire_T_49) @[Cat.scala 33:92]
                         resWire <= _resWire_T_50 @[ALU.scala 126:19]
                       else :
@@ -727,48 +727,48 @@ circuit SingleCycleCPU :
           node _T_11 = eq(UInt<1>("h0"), io.bitType) @[DataMemory.scala 85:28]
           when _T_11 : @[DataMemory.scala 85:28]
             node _readDataMasked_T = mux(UInt<1>("h0"), UInt<56>("hffffffffffffff"), UInt<56>("h0")) @[Bitwise.scala 77:12]
-            node _readDataMasked_T_1 = bits(readDataIntercept, 7, 0) @[CPUUtils.scala 115:36]
+            node _readDataMasked_T_1 = bits(readDataIntercept, 7, 0) @[CPUUtils.scala 118:36]
             node _readDataMasked_T_2 = cat(_readDataMasked_T, _readDataMasked_T_1) @[Cat.scala 33:92]
             readDataMasked <= _readDataMasked_T_2 @[DataMemory.scala 86:40]
           else :
             node _T_12 = eq(UInt<1>("h1"), io.bitType) @[DataMemory.scala 85:28]
             when _T_12 : @[DataMemory.scala 85:28]
               node _readDataMasked_T_3 = mux(UInt<1>("h0"), UInt<48>("hffffffffffff"), UInt<48>("h0")) @[Bitwise.scala 77:12]
-              node _readDataMasked_T_4 = bits(readDataIntercept, 15, 0) @[CPUUtils.scala 115:36]
+              node _readDataMasked_T_4 = bits(readDataIntercept, 15, 0) @[CPUUtils.scala 118:36]
               node _readDataMasked_T_5 = cat(_readDataMasked_T_3, _readDataMasked_T_4) @[Cat.scala 33:92]
               readDataMasked <= _readDataMasked_T_5 @[DataMemory.scala 88:28]
             else :
               node _T_13 = eq(UInt<2>("h2"), io.bitType) @[DataMemory.scala 85:28]
               when _T_13 : @[DataMemory.scala 85:28]
                 node _readDataMasked_T_6 = mux(UInt<1>("h0"), UInt<32>("hffffffff"), UInt<32>("h0")) @[Bitwise.scala 77:12]
-                node _readDataMasked_T_7 = bits(readDataIntercept, 31, 0) @[CPUUtils.scala 115:36]
+                node _readDataMasked_T_7 = bits(readDataIntercept, 31, 0) @[CPUUtils.scala 118:36]
                 node _readDataMasked_T_8 = cat(_readDataMasked_T_6, _readDataMasked_T_7) @[Cat.scala 33:92]
                 readDataMasked <= _readDataMasked_T_8 @[DataMemory.scala 91:28]
         else :
           node _T_14 = eq(UInt<1>("h0"), io.bitType) @[DataMemory.scala 95:28]
           when _T_14 : @[DataMemory.scala 95:28]
-            node readDataMasked_sign = bits(readDataIntercept, 7, 7) @[CPUUtils.scala 114:33]
+            node readDataMasked_sign = bits(readDataIntercept, 7, 7) @[CPUUtils.scala 117:33]
             node _readDataMasked_T_9 = bits(readDataMasked_sign, 0, 0) @[Bitwise.scala 77:15]
             node _readDataMasked_T_10 = mux(_readDataMasked_T_9, UInt<56>("hffffffffffffff"), UInt<56>("h0")) @[Bitwise.scala 77:12]
-            node _readDataMasked_T_11 = bits(readDataIntercept, 7, 0) @[CPUUtils.scala 115:36]
+            node _readDataMasked_T_11 = bits(readDataIntercept, 7, 0) @[CPUUtils.scala 118:36]
             node _readDataMasked_T_12 = cat(_readDataMasked_T_10, _readDataMasked_T_11) @[Cat.scala 33:92]
             readDataMasked <= _readDataMasked_T_12 @[DataMemory.scala 96:40]
           else :
             node _T_15 = eq(UInt<1>("h1"), io.bitType) @[DataMemory.scala 95:28]
             when _T_15 : @[DataMemory.scala 95:28]
-              node readDataMasked_sign_1 = bits(readDataIntercept, 15, 15) @[CPUUtils.scala 114:33]
+              node readDataMasked_sign_1 = bits(readDataIntercept, 15, 15) @[CPUUtils.scala 117:33]
               node _readDataMasked_T_13 = bits(readDataMasked_sign_1, 0, 0) @[Bitwise.scala 77:15]
               node _readDataMasked_T_14 = mux(_readDataMasked_T_13, UInt<48>("hffffffffffff"), UInt<48>("h0")) @[Bitwise.scala 77:12]
-              node _readDataMasked_T_15 = bits(readDataIntercept, 15, 0) @[CPUUtils.scala 115:36]
+              node _readDataMasked_T_15 = bits(readDataIntercept, 15, 0) @[CPUUtils.scala 118:36]
               node _readDataMasked_T_16 = cat(_readDataMasked_T_14, _readDataMasked_T_15) @[Cat.scala 33:92]
               readDataMasked <= _readDataMasked_T_16 @[DataMemory.scala 97:40]
             else :
               node _T_16 = eq(UInt<2>("h2"), io.bitType) @[DataMemory.scala 95:28]
               when _T_16 : @[DataMemory.scala 95:28]
-                node readDataMasked_sign_2 = bits(readDataIntercept, 31, 31) @[CPUUtils.scala 114:33]
+                node readDataMasked_sign_2 = bits(readDataIntercept, 31, 31) @[CPUUtils.scala 117:33]
                 node _readDataMasked_T_17 = bits(readDataMasked_sign_2, 0, 0) @[Bitwise.scala 77:15]
                 node _readDataMasked_T_18 = mux(_readDataMasked_T_17, UInt<32>("hffffffff"), UInt<32>("h0")) @[Bitwise.scala 77:12]
-                node _readDataMasked_T_19 = bits(readDataIntercept, 31, 0) @[CPUUtils.scala 115:36]
+                node _readDataMasked_T_19 = bits(readDataIntercept, 31, 0) @[CPUUtils.scala 118:36]
                 node _readDataMasked_T_20 = cat(_readDataMasked_T_18, _readDataMasked_T_19) @[Cat.scala 33:92]
                 readDataMasked <= _readDataMasked_T_20 @[DataMemory.scala 98:40]
     io.readData <= readDataMasked @[DataMemory.scala 105:15]
@@ -1298,7 +1298,7 @@ circuit SingleCycleCPU :
   module SingleCycleCPU :
     input clock : Clock
     input reset : UInt<1>
-    output io : { isValidInst : UInt<1>, pc : UInt<64>, nextPC : UInt<64>, inst : UInt<32>, aluOperation : UInt<6>, imm : UInt<64>, resultALU : UInt<64>, opcode : UInt<7>, isTrue : UInt<1>, isJALR : UInt<1>, isBType : UInt<1>, isJump : UInt<1>, immALUToReg : UInt<1>, memRead : UInt<1>, memWrite : UInt<1>, immRs2ToALU : UInt<1>, aluY : UInt<64>, pcRs1ToALU : UInt<1>, aluX : UInt<64>, isIType : UInt<1>, isRType : UInt<1>, isWord : UInt<1>, ifWriteToReg : UInt<1>, rs1 : UInt<5>, readDataRs1 : UInt<64>, rs2 : UInt<5>, readDataRs2 : UInt<64>, rd : UInt<5>, resultToReg : UInt<64>, bitType : UInt<2>, isUnsigned : UInt<1>, readData : UInt<64>, regAll : UInt<64>[32]}
+    output io : { isValidInst : UInt<1>, pc : UInt<64>, nextPC : UInt<64>, inst : UInt<32>, aluOperation : UInt<6>, imm : UInt<64>, aluResult : UInt<64>, opcode : UInt<7>, isTrue : UInt<1>, isJALR : UInt<1>, isBType : UInt<1>, isJump : UInt<1>, immALUToReg : UInt<1>, memRead : UInt<1>, memWrite : UInt<1>, immRs2ToALU : UInt<1>, aluY : UInt<64>, pcRs1ToALU : UInt<1>, aluX : UInt<64>, isIType : UInt<1>, isRType : UInt<1>, isWord : UInt<1>, ifWriteToReg : UInt<1>, rs1 : UInt<5>, readDataRs1 : UInt<64>, rs2 : UInt<5>, readDataRs2 : UInt<64>, rd : UInt<5>, resultToReg : UInt<64>, bitType : UInt<2>, isUnsigned : UInt<1>, readData : UInt<64>, regAll : UInt<64>[32]}
 
     inst pcReg of PCReg @[SingleCycleCPU.scala 83:21]
     pcReg.clock <= clock
@@ -1341,7 +1341,7 @@ circuit SingleCycleCPU :
     io.inst <= instMemory.io.inst @[SingleCycleCPU.scala 100:11]
     io.resultToReg <= resSelectUnit.io.out @[SingleCycleCPU.scala 101:18]
     io.readData <= dataMemory.io.readData @[SingleCycleCPU.scala 102:15]
-    io.resultALU <= alu.io.result @[SingleCycleCPU.scala 103:16]
+    io.aluResult <= alu.io.result @[SingleCycleCPU.scala 103:16]
     io.isTrue <= pcSelectUnit.io.isTrue @[SingleCycleCPU.scala 105:13]
     io.opcode <= controlUnit.io.opcode @[SingleCycleCPU.scala 106:13]
     io.isJALR <= controlUnit.io.isJALR @[SingleCycleCPU.scala 107:13]

generated/SingleCycleCPUSimlify/SingleCycleCPUSimlify.anno.json

+[
+  {
+    "class":"firrtl.transforms.DedupedResult",
+    "original":"~SingleCycleCPUSimlify|Adder",
+    "duplicate":"~SingleCycleCPUSimlify|SingleCycleCPUSimlify/pcAdd4:Adder",
+    "index":0.08333333333333333
+  },
+  {
+    "class":"firrtl.transforms.DedupedResult",
+    "original":"~SingleCycleCPUSimlify|Adder_1",
+    "duplicate":"~SingleCycleCPUSimlify|SingleCycleCPUSimlify/pcAddImm:Adder",
+    "index":0.16666666666666666
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"generated/SingleCycleCPUSimlify"
+  }
+]
\ No newline at end of file

src/main/scala/CPU/CPUConfig.scala

@@ -78,7 +78,7 @@ object CPUConfig {
  * <p>
  */
 object DebugControl {
-  /* 组件 IO 打印信息控制 */
+  /* 组件打印信息控制 */
   val ALUIOPrint = false
   val ALUControlUnitIOPrint = false
   val ControlUnitIOPrint = false
@@ -90,8 +90,19 @@ object DebugControl {
   val RegUnitIOPrint = false
   val ResSelectUnitIOPrint = false
 
+  /* 流水线寄存器组打印信息控制 */
+  val IFIDStageRegsIOPrint = false
+  val IDEXEStageRegsIOPrint = false
+  val EXEMEMStageRegsIOPrint = false
+  val MEMWBStageRegsIOPrint = false
+
+  /* 流水线控制器打印信息控制 */
+  val BranchControlUnitIOPrint = false
+  val DataControlUnitIOPrint = false
+
   /* CPU 打印信息控制 */
   val SingleCycleCPUPrint = false
+  val PiplineCPUPrint = false
   val RegPrint = false // 32 个寄存器状态打印
 }
 

src/main/scala/CPU/CPUUtils.scala

@@ -96,10 +96,10 @@ object CPUPrintf {
         cf"${data.asUInt}"
       else
         cf"${data.asUInt}  (0x${Hexadecimal(data.asUInt)})"
-
     }
+
     printf(
-      cf"\t${data.toString().split(":")(0).split('.').last}\t= ${s}\n"
+      cf"\t${data.toString().split(":")(0).replace(".out.", ".[out]").replace(".in.", ".[in]").split('.').last}\t= ${s}\n"
     )
   }
 

src/main/scala/CPU/Componts/RegUnit.scala

@@ -5,6 +5,33 @@ import chisel3.util._
 import CPU.CPUConfig._
 import CPU._
 
+/**
+  * 单周期不允许写时读, 否则会产生回环
+  *
+  */
+class RegUnit() extends RegUnitNormal {
+  readDataRs1 := regGroup(io.rs1)
+  readDataRs2 := regGroup(io.rs2)
+}
+
+/**
+  * 带读写转发版本, 供多周期使用
+  *
+  */
+class RegUnitWithForwarding() extends RegUnitNormal {
+  readDataRs1 := Mux(
+    (io.writeEnable && (io.rs1 === io.rd)),
+    io.writeData,
+    regGroup(io.rs1)
+  )
+
+  readDataRs2 := Mux(
+    (io.writeEnable && (io.rs2 === io.rd)),
+    io.writeData,
+    regGroup(io.rs2)
+  )
+}
+
 /**
  * <b>[[寄存器单元]]</b>
  * <p>
@@ -23,7 +50,7 @@ import CPU._
  *   - readDataRs1 : 从 rs1 中读出的数据
  *   - readDataRs2 : 从 rs2 中读出的数据
  */
-class RegUnit extends Module {
+class RegUnitNormal() extends Module {
   val io = IO(new Bundle {
     /* input */
     val rs1 = Input(UInt(5.W))
@@ -46,22 +73,38 @@ class RegUnit extends Module {
 
   val regGroup = RegInit(VecInit(regInitSeq))
 
-  // X0 读出的数据为 0
-  io.readDataRs1 := Mux(io.rs1 === 0.U, 0.U, regGroup(io.rs1))
-  io.readDataRs2 := Mux(io.rs2 === 0.U, 0.U, regGroup(io.rs2))
+  val readDataRs1 = WireDefault(0.U(XLEN.W))
+  val readDataRs2 = WireDefault(0.U(XLEN.W))
 
-  // 此处不允许写时读, 否则会产生回环
+  // // 单周期不允许写时读, 否则会产生回环
+  // // 多周期允许
   // // 考虑写时读的问题, 读写转发
-  // io.readDataRs1 := Mux(
-  //   (io.writeEnable && (io.rs1 === io.rd)),
-  //   io.writeData,
-  //   regGroup(io.rs1)
-  // )
-  // io.readDataRs2 := Mux(
-  //   (io.writeEnable && (io.rs2 === io.rd)),
-  //   io.writeData,
-  //   regGroup(io.rs2)
-  // )
+  // when(io.forwarding === true.B) {
+  //   readDataRs1 := Mux(
+  //     (io.writeEnable && (io.rs1 === io.rd)),
+  //     io.writeData,
+  //     regGroup(io.rs1)
+  //   )
+
+  //   readDataRs2 := Mux(
+  //     (io.writeEnable && (io.rs2 === io.rd)),
+  //     io.writeData,
+  //     regGroup(io.rs2)
+  //   )
+  // }.otherwise {
+  //   readDataRs1 := regGroup(io.rs1)
+  //   readDataRs2 := regGroup(io.rs2)
+  // }
+
+  // X0 读出的数据为 0
+  io.readDataRs1 := Mux(io.rs1 === 0.U, 0.U, readDataRs1)
+  io.readDataRs2 := Mux(io.rs2 === 0.U, 0.U, readDataRs2)
+
+  // printf(cf"[DEBUG] sp = ${Decimal(regGroup(2.U))}\n")
+  // printf(cf"[DEBUG] readDataRs1 = ${Decimal(readDataRs1)}\n")
+  // printf(cf"[DEBUG] readDataRs2 = ${Decimal(readDataRs2)}\n")
+  // printf(cf"[DEBUG] Rs1 = ${Decimal(io.readDataRs1)}\n")
+  // printf(cf"[DEBUG] Rs2 = ${Decimal(io.readDataRs2)}\n")
 
   // x0 不允许写
   when(io.writeEnable === true.B && io.rd =/= 0.U) {
@@ -83,7 +126,7 @@ class RegUnit extends Module {
     List(io.writeData, io.readDataRs1, io.readDataRs2, rs1UInt, rs2UInt, rdUInt)
   val needHex = List()
   val needBool = io.getElements.filter(data => data.isInstanceOf[Bool]).toList
-  val needDelete = List(io.rs1, io.rs2, io.rd)
+  val needDelete = List(io.rs1, io.rs2, io.rd, io.regAll)
   val needAdd = List(rs1UInt, rs2UInt, rdUInt)
 
   if (DebugControl.RegUnitIOPrint) {

src/main/scala/CPU/PiplineComponts/EXEMEMStageRegs.scala

+package CPU.PiplineComponts
+
+import chisel3._
+
+import CPU._
+import CPU.CPUPrintf
+import CPUConfig._
+
+class EXEMEMStageRegsIO extends Bundle {
+  val pc = UInt(XLEN.W) // PC
+  val inst = UInt(INST_W.W) // 指令
+
+  // 控制信号
+  val isJump = Bool()
+  val immALUToReg = Bool()
+  val memRead = Bool()
+  val memWrite = Bool()
+  val writeEnable = Bool()
+
+  // 寄存器组
+  val readDataRs2 = UInt(XLEN.W)
+  val rd = UInt(5.W)
+
+  // ALU 计算结果
+  val aluResult = UInt(XLEN.W)
+
+  // 立即数
+  val imm = UInt(XLEN.W)
+}
+
+class EXEMEMStageRegs extends GeneralStageRegs(new EXEMEMStageRegsIO) {
+
+  // **************** print **************** //
+  val needBinary =
+    List(io.in.inst, io.out.inst)
+  val needDec = List(
+    io.in.readDataRs2,
+    io.out.readDataRs2,
+    io.in.imm,
+    io.out.imm,
+    io.in.aluResult,
+    io.out.aluResult
+  )
+  val needHex = List(io.in.pc, io.out.pc)
+  val needBool = List[Bool]()
+    .appendedAll(io.getElements.filter(data => data.isInstanceOf[Bool]))
+    .appendedAll(io.in.getElements.filter(data => data.isInstanceOf[Bool]))
+    .appendedAll(io.out.getElements.filter(data => data.isInstanceOf[Bool]))
+
+  val needDelete = List(io.in, io.out)
+  val needAdd = List[Data]()
+    .appendedAll(io.out.getElements)
+    .appendedAll(io.in.getElements)
+
+  if (DebugControl.EXEMEMStageRegsIOPrint) {
+    CPUPrintf.printfIO(
+      "INFO",
+      this,
+      io.getElements
+        .filterNot(data => needDelete.contains(data))
+        .toList
+        .appendedAll(needAdd),
+      needBinary,
+      needDec,
+      needHex,
+      needBool
+    )
+  }
+}