This project is mirrored from https://github.com/Xilinx/u-boot-xlnx.git.
Pull mirroring updated .
- Apr 17, 2012
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Jagan Teki authored
New configuration file is added for XM013,by keeping XM010 configs as it is. Tested on zc770-21, -34 boards. Signed-off-by: Jagan <jaganna@xilinx.com>
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- Apr 12, 2012
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Jagan Teki authored
This patch enables STMICRO, WINBOND and SPANSION QSPI's by default. Signed-off-by: Jagan <jaganna@xilinx.com>
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Jagan Teki authored
This patch adds a support for S25FL129P with x2 device. for building x2 QSPI, please uncomment CONFIG_XILINX_PSS_QSPI_USE_DUAL_FLASH on include/configs/xpele.h This was tested on the ep107-11 board. Signed-off-by: Jagan <jaganna@xilinx.com>
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Jagan Teki authored
This patch adds a support for S25FL129P with x1 device. This was tested on the ep107-11 board. Signed-off-by: Jagan <jaganna@xilinx.com>
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Jagan Teki authored
This patch adds a support for W25Q64DW with x1 device. This was tested on the ep107-2 board. Signed-off-by: Jagan <jaganna@xilinx.com>
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- Apr 11, 2012
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Jun Flores JR authored
This updates the top-level make file to add zynq_cseflash_config target. This is needed to support QSPI programming from the Xilinx tools. A new header file, zynq_cseflash.h, is also added so that u-boot can be configured to build using the zynq_cseflash_config target.
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- Mar 05, 2012
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John Linn authored
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John Linn authored
New board configurations are needed to allow EP107 to not be broken, and to allow each board to be configured differently. zynq_zc770_config and zynq_zc702_config are now new make targets.
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John Linn authored
The previous fix, including xpele.h, worked for EP107, but doesn't work once there are more configuation header files other than xpele.h. This now works for new ones also.
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- Mar 04, 2012
- Jan 18, 2012
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GIT Repo authored
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John Linn authored
This commit is intended to be reverted once all the boards are patched so that Gb works. Until then, stay at 100 Mb. This allowed the previous work to be checked in so that it's ready.
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Andrei Simion authored
On EP107, U-boot can now communicate over ethernet at 10 and 100 Mbps.
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Andrei Simion authored
MAC/PHY driver has been cleaned up and commented thoroughly. Uneeded code has been removed.
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Andrei Simion authored
The PHY driver has been updated to establish a link at the highest speed possible. The GEM divisors are modified to create an input frequency that matches the link speed: 2.5MHz for 10Mbps 25MHz for 100Mbps 125MHz for 1000Mbps Error checking has also been included to prevent auto-negotiation from stalling and for catching failed auto-negotiation attempts.
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GIT Repo authored
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John Linn authored
To make it easier for developers in jtag mode, make it automatically TFTP a kernel into memory and start it.
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- Jan 06, 2012
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John Linn authored
With the newer GNU tools, GCC 4.5.2 and newer, we're seeing data aborts. This solution may not be the right long term solution, but works for now. This causes GCC not to generate unaligned data.
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John Linn authored
With the newer GNU tools, GCC 4.5.2 and newer, we're seeing data aborts. This solution may not be the right long term solution, but works for now. This causes GCC not to generate unaligned data.
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John Linn authored
With the newer GNU tools, GCC 4.5.2 and newer, we're seeing data aborts. This solution may not be the right long term solution, but works for now. This causes GCC not to generate unaligned data.
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- Dec 21, 2011
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John Linn authored
The NAND working caused u-boot to lockup when there was no NAND so now there's CONFIGs for each board permutation of the ZC770. The default is for DC1 (XM010) card.
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- Dec 20, 2011
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John Linn authored
When moving from PEEP to Zynq, the ID of the flash was not being read at all, only zeroes. The driver was not waiting for the device to be ready after resetting the device and since Zynq is so much faster it was a problem.
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- Dec 14, 2011
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John Linn authored
SD boot was not supported in the automatic boot mode, now it is. Even though this loads a ramdisk you can just ignore the ramdisk if the root file system is on SD in an EXT2 file system.
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John Linn authored
In the former change, a divisor too low seems cause problems with the lower speed cards. This is attempt to have something that's tolerable even if it's not the optimal. This allows the kernel and ramdisk to be loaded reasonably quickly.
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John Linn authored
Temporary hack to take USB out of reset til Linux is fixed.
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John Linn authored
It's not clear why it was was running so slow, but maybe it was needed for EP107. Speed it up now.
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- Dec 08, 2011
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John Linn authored
This is a hack to compensate for Linux not having the PHY updated yet as u-boot needs to touch the PHY for Linux networking to work.
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- Dec 04, 2011
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John Linn authored
This should allow u-boot to be built for the zc770 and work with the default FSBL which setups up the DDR, PLLs, and MIO for 800 MHz CPU, 533 MHz DDR. UART and Ethernet are working at this point.
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- Dec 02, 2011
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John Linn authored
This header file was needed for the commit (a ways back) that added PLL init to the board.c file.
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- Nov 30, 2011
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John Linn authored
Only minor changes to GEM assuming MIO and IO PL are setup somewhere else (FSBL or a script). The DC1 PHY needs some help to work on the ZC770 and that was added. Since Zynq is much faster than EP107, removed some of the printing of "." which was too much.
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John Linn authored
The EP107 is now not the default build.
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John Linn authored
This should not be needed as FSBL will be doing it. The DDR init was causing a hang and was not needed anyway.
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John Linn authored
The memory barriers appeared to be wrong, this moves the barriers to be correct.
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John Linn authored
The 100 Mb mode needs a 25 MHz clock input so this was needed for this testing.
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John Linn authored
This should not live on and is only temporary til FSBL is working.
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- Nov 22, 2011
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- Nov 17, 2011
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Andrei Simion authored
If CONFIG_EP107 is defined, include 'xparameters.h' and 'xparameters_pss.h', otherwise include 'xparameters_zynq.h' and 'xparameters_pss_zynq.h'. The Zynq variants of xparameters are subject to change. For now, the only difference is XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ is 216664500 Hz instead of 12500000 Hz and XPAR_XUARTPSS_1_CLOCK_HZ is 13756480 Hz instead of 50000000 Hz to reflect silicon.
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Andrei Simion authored
U-boot's configuration environment will reside in NOR flash only if CONFIG_EP107 is defined.
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