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ward
Istyle Verilog Formatter

I

Istyle Verilog Formatter

Project information

Open source implementation of a Verilog formatter

38 Commits
3 Branches
2 Tags

README
GNU General Public License v2.0 or later

Created on

June 05, 2020

Copy SSH clone URLgit@git.nju.edu.cn:ward/istyle-verilog-formatter.git
Copy HTTPS clone URLhttps://git.nju.edu.cn/ward/istyle-verilog-formatter.git