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  1. 23 9月, 2022 1 次提交
  2. 15 9月, 2022 2 次提交
  3. 13 9月, 2022 1 次提交
  4. 31 8月, 2022 1 次提交
  5. 29 7月, 2022 1 次提交
  6. 20 7月, 2022 1 次提交
  7. 19 7月, 2022 5 次提交
  8. 18 7月, 2022 1 次提交
    • Ahmed Charles's avatar
      RISC-V PTE compliance · f2bbbb20
      Ahmed Charles 创作于
      The RISC-V Instruction Set Manual - Volume II: Privileged Architecture:
      For non-leaf PTEs, the D, A, and U bits are reserved for future standard
      use. Until their use is defined by a standard extension, they must be
      cleared by software for forward compatibility.
      Signed-off-by: default avatarAhmed Charles <>
  9. 29 6月, 2022 1 次提交
  10. 20 6月, 2022 1 次提交
  11. 17 6月, 2022 1 次提交
    • Ryan Barry's avatar
      Don't clobber msgInfo register · 4ce6cbe9
      Ryan Barry 创作于
      The messageinfo register is set to 0 after processing a kernel object
      invocation if the invocation set the thread state to restart. This is a
      problem if the kernel object invocation had also set the message info
      The existing convention in this case is for the kernel invocation to
      set the thread state to running right before it returns to avoid the
      problematic code path. However, there are some invocations that do not
      follow this convention and their message info register gets clobbered.
      There are also some invocations that set message registers without
      setting the message info register at all, or that do not guard their
      message register updates with a call parameter.
      This commit fixes these issues modulo setConsumed, which we defer to a
      later point.
      Co-authored-by: default avatarJimmy Brush <>
      Signed-off-by: default avatarRyan Barry <>
  12. 06 6月, 2022 2 次提交
    • Rafal Kolanski's avatar
      arm: don't do S1 translation in Arch_setMRs_fault · b8ef00e0
      Rafal Kolanski 创作于
      For a VM fault in a hypervisor context, 32-bit Arm translated the IP
      address into an IPA, while 64-bit Arm did not. The previous commit
      made these consistent by performing the translation on both.
      After investigation and discussion, the 32-bit Arm behaviour was
      declared a bug: reporting an IPA (instead of a VA) to the VMM is not
      very useful and can cause issues when the fault message is not sent
      immediately (SELFOUR-1602). This commit, therefore, removes all stage 1
      translation from Arch_setMRs_fault on Arm platforms.
      Signed-off-by: default avatarRafal Kolanski <>
    • Rafal Kolanski's avatar
      arm: consolidate stage 1 translation function use · fce5cece
      Rafal Kolanski 创作于
      This commit introduces `addressTranslateS1` to be used on Arm platforms
      with hypervisor enabled for stage 1 (vaddr to IPA) translation. On
      AArch32 this is a rename from `addressTranslateS1CPR`, and on AArch64 it
      wraps `ats1e1r`. This changes the ABI on AArch64 to report faulting
      address as IPA.
      With hypervisor enabled, AArch64 defined `addressTranslateS1CPR` to do
      nothing, while AArch32 defined it to do stage 1 translation. This
      delivered VM faults to the user with the faulting address being either
      an IPA or a vaddr depending on mode. This inconsistency is undesireable.
      This commit proposes adjusting the inconsistency to match AArch32
      behaviour, as it is one of the verified platforms.
      Signed-off-by: default avatarRafal Kolanski <>
  13. 03 6月, 2022 3 次提交
  14. 27 5月, 2022 1 次提交
    • Matthew Brecknell's avatar
      Add config option to prevent cloned functions · 812c0c2a
      Matthew Brecknell 创作于
      Some inter-procedural optimisations can produce cloned or partial
      functions in the binary. Since binary verification is incompatible with
      cloned and partial functions, we add a config option to disable these
      This does not change any defaults, so to avoid cloned and partial
      functions for a binary verification build, it is necessary to explicitly
      configure this, e.g. using `-DKernelBinaryVerificationBuild=ON`.
      Signed-off-by: default avatarMatthew Brecknell <>
  15. 23 5月, 2022 3 次提交
  16. 20 5月, 2022 6 次提交
  17. 19 5月, 2022 1 次提交
  18. 18 5月, 2022 2 次提交
  19. 12 5月, 2022 3 次提交
  20. 11 5月, 2022 2 次提交
  21. 02 5月, 2022 1 次提交