diff --git a/include/arch/arm/arch/32/mode/kernel/vspace.h b/include/arch/arm/arch/32/mode/kernel/vspace.h index 768ff741f69dbab3a53ef37f57ddbf760d741fc6..f7619a6dab9d5e388512a5e63c23f91254b93ff7 100644 --- a/include/arch/arm/arch/32/mode/kernel/vspace.h +++ b/include/arch/arm/arch/32/mode/kernel/vspace.h @@ -70,7 +70,7 @@ bool_t CONST isIOSpaceFrameCap(cap_t cap); static const region_t BOOT_RODATA mode_reserved_region[] = { { (PD_ASID_SLOT + 0) << ARMSectionBits, - (PD_ASID_SLOT + 1) << ARMSectionBits + (PD_ASID_SLOT + 1) << ARMSectionBits } }; diff --git a/include/arch/riscv/arch/encoding.h b/include/arch/riscv/arch/encoding.h index ddb365e551247ffa9a1b9d4b5c0e2aaf6c192a33..1f3465dac9d49d2f344123ffcd92ee605cc1e174 100644 --- a/include/arch/riscv/arch/encoding.h +++ b/include/arch/riscv/arch/encoding.h @@ -1001,8 +1001,8 @@ DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) -DECLARE_INSN( or , MATCH_OR, MASK_OR) -DECLARE_INSN( and , MATCH_AND, MASK_AND) +DECLARE_INSN( or, MATCH_OR, MASK_OR) +DECLARE_INSN( and, MATCH_AND, MASK_AND) DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) diff --git a/src/arch/arm/32/kernel/vspace.c b/src/arch/arm/32/kernel/vspace.c index 27dc14052e6c403ce301cf6e071891a4fc88a4b6..fce95a2758fcc31865b0390007b6932873fd2559 100644 --- a/src/arch/arm/32/kernel/vspace.c +++ b/src/arch/arm/32/kernel/vspace.c @@ -2947,7 +2947,7 @@ decodeARMMMUInvocation(word_t invLabel, word_t length, cptr_t cptr, } pool = armKSASIDTable[cap_asid_pool_cap_get_capASIDBase(cap) >> - asidLowBits]; + asidLowBits]; if (unlikely(!pool)) { userError("ASIDPoolAssign: Failed to lookup pool."); current_syscall_error.type = seL4_FailedLookup; diff --git a/src/arch/arm/machine/l2c_310.c b/src/arch/arm/machine/l2c_310.c index 6b23461b8b7e1fb579d80f7a6574a03d721fb1d7..bd06ec9718ee3c604eba299086bc0fc7d67cd94e 100644 --- a/src/arch/arm/machine/l2c_310.c +++ b/src/arch/arm/machine/l2c_310.c @@ -288,7 +288,7 @@ initL2Cache(void) /* Access secure registers through Security Middleware Call */ /* 1: Write to aux Tag RAM latentcy, Data RAM latency, prefect, power control registers */ mshield_smc(MSHIELD_SMC_ROM_CTRL_CTRL, 0, 0); - mshield_smc(MSHIELD_SMC_ROM_CTRL_AUX , aux, 0); + mshield_smc(MSHIELD_SMC_ROM_CTRL_AUX, aux, 0); mshield_smc(MSHIELD_SMC_ROM_CTRL_LATENCY, tag_ram, data_ram); #else /* !TI_MSHIELD */