From 466455f37b94cf785db7a3512992ae86a1f834a8 Mon Sep 17 00:00:00 2001
From: Kent McLeod <Kent.Mcleod@data61.csiro.au>
Date: Thu, 21 Feb 2019 11:12:28 +1100
Subject: [PATCH] gic: Move common GIC definitions to shared header
Share definitions between gic_pl390.h and gic_v3.h.
---
include/arch/arm/arch/machine/gic_common.h | 47 ++++++++++++++++++++++
include/arch/arm/arch/machine/gic_pl390.h | 21 +---------
include/arch/arm/arch/machine/gic_v3.h | 21 +---------
src/arch/arm/machine/gic_pl390.c | 5 ---
src/arch/arm/machine/gic_v3.c | 5 ---
5 files changed, 49 insertions(+), 50 deletions(-)
create mode 100644 include/arch/arm/arch/machine/gic_common.h
diff --git a/include/arch/arm/arch/machine/gic_common.h b/include/arch/arm/arch/machine/gic_common.h
new file mode 100644
index 000000000..81c4d493e
--- /dev/null
+++ b/include/arch/arm/arch/machine/gic_common.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2019, Data61
+ * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
+ * ABN 41 687 119 230.
+ *
+ * This software may be distributed and modified according to the terms of
+ * the GNU General Public License version 2. Note that NO WARRANTY is provided.
+ * See "LICENSE_GPLv2.txt" for details.
+ *
+ * @TAG(DATA61_GPL)
+ */
+
+#ifndef __ARCH_MACHINE_GIC_COMMON_H
+#define __ARCH_MACHINE_GIC_COMMON_H
+
+#include <stdint.h>
+
+/* Shift positions for GICD_SGIR register */
+#define GICD_SGIR_SGIINTID_SHIFT 0
+#define GICD_SGIR_CPUTARGETLIST_SHIFT 16
+#define GICD_SGIR_TARGETLISTFILTER_SHIFT 24
+
+
+typedef uint16_t interrupt_t;
+typedef uint16_t irq_t;
+
+enum irqNumbers {
+ irqInvalid = (irq_t) - 1
+};
+
+/*
+ * The only sane way to get an GIC IRQ number that can be properly
+ * ACKED later is through the int_ack register. Unfortunately, reading
+ * this register changes the interrupt state to pending so future
+ * reads will not return the same value For this reason, we have a
+ * global variable to store the IRQ number.
+ */
+extern uint32_t active_irq[CONFIG_MAX_NUM_NODES];
+
+static inline void handleSpuriousIRQ(void)
+{
+}
+
+void initIRQController(void);
+
+
+#endif /* __ARCH_MACHINE_GIC_COMMON_H */
diff --git a/include/arch/arm/arch/machine/gic_pl390.h b/include/arch/arm/arch/machine/gic_pl390.h
index 914e937c8..2e8e04631 100644
--- a/include/arch/arm/arch/machine/gic_pl390.h
+++ b/include/arch/arm/arch/machine/gic_pl390.h
@@ -23,12 +23,7 @@
#include <mode/smp/smp.h>
#include <model/statedata.h>
-typedef uint16_t interrupt_t;
-typedef uint16_t irq_t;
-
-enum irqNumbers {
- irqInvalid = (irq_t) - 1
-};
+#include "gic_common.h"
/* CPU specific IRQ's */
#define SGI_START 0u
@@ -148,14 +143,6 @@ struct gic_cpu_iface_map {
extern volatile struct gic_dist_map *const gic_dist;
extern volatile struct gic_cpu_iface_map *const gic_cpuiface;
-/*
- * The only sane way to get an GIC IRQ number that can be properly
- * ACKED later is through the int_ack register. Unfortunately, reading
- * this register changes the interrupt state to pending so future
- * reads will not return the same value For this reason, we have a
- * global variable to store the IRQ number.
- */
-extern uint32_t active_irq[CONFIG_MAX_NUM_NODES];
/* Helpers */
static inline int is_irq_edge_triggered(irq_t irq)
@@ -235,12 +222,6 @@ static inline void ackInterrupt(irq_t irq)
}
-static inline void handleSpuriousIRQ(void)
-{
-}
-
-void initIRQController(void);
-
#ifdef ENABLE_SMP_SUPPORT
void ipiBroadcast(irq_t irq, bool_t includeSelfCPU);
void ipi_send_target(irq_t irq, word_t cpuTargetList);
diff --git a/include/arch/arm/arch/machine/gic_v3.h b/include/arch/arm/arch/machine/gic_v3.h
index 58877ab87..8bb477701 100644
--- a/include/arch/arm/arch/machine/gic_v3.h
+++ b/include/arch/arm/arch/machine/gic_v3.h
@@ -28,12 +28,7 @@
#include <model/statedata.h>
#include <armv/machine.h>
-typedef uint16_t interrupt_t;
-typedef uint16_t irq_t;
-
-enum irqNumbers {
- irqInvalid = (irq_t) - 1
-};
+#include "gic_common.h"
/* Special IRQ's */
#define SPECIAL_IRQ_START 1020u
@@ -182,14 +177,6 @@ struct gic_rdist_sgi_ppi_map { /* Starting */
extern volatile struct gic_dist_map *const gic_dist;
extern volatile struct gic_rdist_map *gic_rdist_map[CONFIG_MAX_NUM_NODES];
extern volatile struct gic_rdist_sgi_ppi_map *gic_rdist_sgi_ppi_map[CONFIG_MAX_NUM_NODES];
-/*
- * The only sane way to get an GIC IRQ number that can be properly
- * ACKED later is through the int_ack register. Unfortunately, reading
- * this register changes the interrupt state to pending so future
- * reads will not return the same value For this reason, we have a
- * global variable to store the IRQ number.
- */
-extern uint32_t active_irq[CONFIG_MAX_NUM_NODES];
static inline bool_t is_sgi(irq_t irq)
@@ -314,12 +301,6 @@ static inline void ackInterrupt(irq_t irq)
}
-static inline void handleSpuriousIRQ(void)
-{
-}
-
-void initIRQController(void);
-
#ifdef ENABLE_SMP_SUPPORT
void ipiBroadcast(irq_t irq, bool_t includeSelfCPU);
void ipi_send_target(irq_t irq, word_t cpuTargetList);
diff --git a/src/arch/arm/machine/gic_pl390.c b/src/arch/arm/machine/gic_pl390.c
index 7522b3781..86ee9e9b0 100644
--- a/src/arch/arm/machine/gic_pl390.c
+++ b/src/arch/arm/machine/gic_pl390.c
@@ -24,11 +24,6 @@
#define IRQ_SET_ALL 0xffffffff;
-/* Shift positions for GICD_SGIR register */
-#define GICD_SGIR_SGIINTID_SHIFT 0
-#define GICD_SGIR_CPUTARGETLIST_SHIFT 16
-#define GICD_SGIR_TARGETLISTFILTER_SHIFT 24
-
#ifndef GIC_PL390_DISTRIBUTOR_PPTR
#error GIC_PL390_DISTRIBUTOR_PPTR must be defined for virtual memory access to the gic distributer
#else /* GIC_DISTRIBUTOR_PPTR */
diff --git a/src/arch/arm/machine/gic_v3.c b/src/arch/arm/machine/gic_v3.c
index e2f72594b..13bc1e309 100644
--- a/src/arch/arm/machine/gic_v3.c
+++ b/src/arch/arm/machine/gic_v3.c
@@ -22,11 +22,6 @@
/* Assume 8 cores */
#define GICR_SIZE (0x100000)
-/* Shift positions for GICD_SGIR register */
-#define GICD_SGIR_SGIINTID_SHIFT 0
-#define GICD_SGIR_CPUTARGETLIST_SHIFT 16
-#define GICD_SGIR_TARGETLISTFILTER_SHIFT 24
-
#define GIC_DEADLINE_MS 2
#define GIC_REG_WIDTH 32
--
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