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  • v20171107
    b4dae89f · Bump GCC ·
    November 7th 2017 Toolchain Release
    
    It's been about two months since the last stable toolchain release, so
    we're a bit past due for a new one.  Here's a summary of the changes
    in this release
    
    * binutils-gdb is still based on the 2.29 upstream release, with the
    following patches:
        * d0176cb1653b ("RISC-V: Fix riscv g++ testsuite EH failures.")
        * d5feabfac32f ("RISC-V: Add satp as an alias for sptbr")
        * 2f9782d95416 ("(WIP SIM): Fix jal and jalr")
        * f64577d1c916 ("RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0")
        * d51d92c4d06b ("RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2")
        * 3593f7f30f80 ("Fix my previous gas/ChangeLog entry")
        * 164a62116dc9 ("RISC-V: Don't emit 2-byte NOPs if the C extension is disabled")
        * 915b00e356e0 ("RISC-V: Relax RISCV_PCREL_* to RISCV_GPREL_*")
        * fa753df2d560 ("RISC-V: Add R_RISCV_DELETE, which marks bytes for deletion")
        * 9eb250cb914c ("RISC-V: Mark unsupported gas testcases")
        * 0d96fbb3095f ("riscv: Cache the max alignment of output sections")
        * 60cda8de81dc ("RISC-V: Avoid emitting invalid instructions in mixed RVC/no-RVC code")
        * 296c682e9d92 ("RISC-V: Print an error when unable to align a section")
        * 1bfb4ecbd84c ("RISC-V: Support PCREL_* relocations agaist weak undefined symbols")
        * d3fae8db583d ("Improve handling of ADD and SUB relocations on the RISCV target.")
        * 404de0666a6a ("RISC-V: Mark "c.nop" as an alias")
        * dfbf9e44a0e1 ("Fix problems parsing RISCV architecture extenstions in the assembler.")
        * 697d5b8ee280 ("(RISC-V GDB) Only save FPRs on harts that support F/D/Q")
        * 495d737e62c0 ("(RISC-V GDB) GDB update")
        * c950de297cd7 ("(RISC-V GDB) RISC-V GDB Port")
        * dd9a28c0966d ("Bump version to 2.29")
    * GCC is now based on the 7.2.0 upstream release, with the following
    patches
        * b731149757b9 ("RISC-V: Implement movmemsi")
        * 605bc7b5e06a ("RISC-V: Define MUSL_DYNAMIC_LINKER")
        * 2423096b0696 ("RISC-V: Emit "i" suffix for instructions with immediate operands")
        * 327d99b09bc0 ("RISC-V: If -m[no-]strict-align is not passed, assume its value from -mtune")
        * f34a83e82258 ("RISC-V: Set SLOW_BYTE_ACCESS=1")
        * 7dde69e2c5f7 ("RISC-V: Handle non-legitimate address in riscv_legitimize_move")
        * 1751fbe7b9e8 ("RISC-V: Use "@minus{}2 GB" instead of "-2 GB" in invoke.texi")
        * 6d1f1f891869 ("RISC-V: Document the medlow and medany code models")
        * d2d1f783b2c1 ("RISC-V: Correct and improve the "-mabi" documentation")
        * d13dd0242604 ("RISC-V: Add Sign/Zero extend patterns for PIC loads")
        * 341375637a7d ("RISC-V: Add -mstrict-align option")
        * f47f9c2b3b90 ("RISC-V: Unify indention in riscv.md")
        * 1bd23ca8c30f ("Update ChangeLog and version files for release")
    
  • v20170612
    b7e00039 · The default ISA is GC ·
    June 12th 2017 Toolchain Release
    
    It's been a month since the last stable toolchain release, which seems like a
    good time for another one. Here's the changes since the last release:
    
    binutils
    * GP-relative disassembly hints are working again.
    * 32-bit BFDs can handle 64-bit objects.
    * c.li, c.andi, and c.addiw disassembly correctly.
    
    gcc
    * A new "-mstrict-align" option is availiable, which enforces strict
      alignment. Without this argument the compiler assumes unaligned operations
      are slow instead of assuming they're illegal. This is meant to be used in
      machine-mode code on platforms that don't support unaligned accesses.
    * Sub-XLEN PIC loads now extend correctly.
    * An internal compiler error related to sub-word moves has been fixed.
      glibc
    * The initial GP generation cannot be relaxed.
    
    newlib
    * We are using a version based on 2.5.
    
    riscv-gnu-toolchain
    * The prerequisite libraries are downloaded correctly again.
    * There is a "--with-guile" flag
    
  • v20170503
    May 3rd 2017 Toolchain Release
    
    As you may have noticed, we recently had an upstream release of GCC that
    contains RISC-V support. Since we're now upstream in binutils and GCC it seems
    like a good time to start tagging releases of riscv-gnu-toolchain as stable.
    I've tagged the current release on github. Since this is a sort of meta-repo,
    I thought the best versioning scheme would just be the current date, so that's
    what I'm going with.
    
    I'll try to regularly tag stable releases of the toolchain. I'm going to just
    play it by ear as to how frequently I release these, but I anticipate it being
    between weekly and monthly. All these tagged release will have passed the
    various test suites we run, and I'll write a change log on all the future
    releases so users don't have to track commits.
    
    Note that just because we've tagged a release doesn't mean things are stable:
    glibc and Linux still aren't upstream so their ABIs aren't set in stone yet
    (though we hope not to have to change them). I'm checking the "This is a
    pre-release" button on GitHib due to possibility of ABI changes.
    
  • v20170818
    August 18th Toolchain Release
    
    It's been about two months singe the last stable toolchain release, so
    we're a bit past new on a new one.  Here's a summary of the changes
    since the June release:
    
    binutils/gdb:
    * Now based on the 2.29 upstream release.
    * 5852e73c72db RISC-V: Support PCREL_* relocations agaist weak
      undefined symbols
    * 0419befe6f92 (WIP) RISC-V: Provide better disassembly of alignment
      sequences
    * 160ba91886e3 (WIP) objdump: Provide the found reloc to the disassembler
    * 779cd1f46451 (WIP) RISC-V: Avoid emitting invalid instructions in mixed
      RVC/no-RVC code
    * ceef952725fb (WIP) RISC-V: Print an error when unable to align a section
    
    We're not including GCC 7.2 here as it's just a bit too new, so there
    are no changes to our GCC port.