GitLab

Upgrade bitmanip v.0.92 to v.0.93, enable simultaneous use with v.1.00

The main changes implemented by this PR are:
1. Support for bitmanip draft v.0.92 is dropped.
2. Remaining bitmanip instructions not ratified as part of v.1.00 of
   the bitmanip spec are upgraded to the latest draft (v.0.93).
3. Simultaneous use of the v.1.00 bitmanip instructions and those
   instructions only part of draft v.0.93 is enabled.
4. Rename bext/bdep to bcompress/bdecompress. This is part of v.0.94.
   But it's needed as in v.0.93 as well as in v.1.00 sbext from Zbs
   is renamed to bext, leading to two completely different instructions
   having the same name.
5. Increase the MAX_INSTR_STR_LEN parameter to accomodate longer
   instruction names (bdecompressw has 12 characters).
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>

Bitmanip v1.0.0 support

Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

Fix typo with fs3_sign value

[PyFlow] Update README.md 

Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>

Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>

Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>

[Pygen]: Add coverage for RV32C instruction

Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>

Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>

Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>

Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>

Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>

[Pygen]: Add gen_timeout for PyFlow

Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>

Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

Fixed length of binary for cases C_FSDSP, C_SDSP, C_SQSP, C_SWSP and C_FSWSP from 17 bits to 16 bits.

In function convert2bin for I & R formats and category == CSR, binary was only 31 bits. Made it to 32 bits by changing csr[10:0] to csr[11:0].

Report job progress like "1/2" and "2/2" instead of "0/2" and "1/2", as
it was done before.

Only a cosmetic change.
Signed-off-by: Philipp Wagner <phw@lowrisc.org>

Signed-off-by: Udi Jonnalagadda <udij@google.com>

Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>

 bug fixes, change ISS to spike in CI regression
Signed-off-by: Aimee Sutton <aimee.sutton@metrics.ca>

Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>

This doesn't seem to be supported by at least Questa 2020.03 (see
issue #780). I don't have a Questa licence or manual locally, but it
looks like this is an Xcelium flag. Maybe it was supported by other
Questa versions as a compatibility shim? If we need to allow the
equivalent access, I think the argument is "+acc", but I'm not
convinced it's needed at all, so suggest removing it entirely.

CI currently fails due to some backend issue,
temporarily disable it on all PRs until a fix
is implemented.

Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>

Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>

Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>

Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>

Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>