Commits · 3d72f3a2c96a5fafc5b1651eaed0b46491e8db7b · Panda / RISC-V DV

This project is mirrored from https://github.com/google/riscv-dv.git. Pull mirroring failed May 24, 2022.
Last successful update May 24, 2022.

28 Oct, 2021 2 commits
- Merge pull request #829 from saurabhsingh-pvips/readme · 3d72f3a2
  Hodjat Asghari Esfeden authored Oct 27, 2021
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[PyFlow] Update README.md 
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  3d72f3a2
- Remove the pyucis-viewer from requirements.txt · ab742b12
  aneels3 authored Oct 27, 2021
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Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>
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  ab742b12
19 Oct, 2021 1 commit
- Update README.md for PyFlow & add pyucis-viewer in requiremen.txt · 07f324ee
  aneels3 authored Oct 18, 2021
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Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>
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  07f324ee
16 Sep, 2021 1 commit
- Merge pull request #815 from saurabhsingh-pvips/rv32c_cov · adfe6f77
  Hodjat Asghari Esfeden authored Sep 16, 2021
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[Pygen]: Add coverage for RV32C instruction
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  adfe6f77
14 Sep, 2021 1 commit
- Add hint_cg and illegal_compressed_instr_cg covergroups · 3ddeb0a6
  aneels3 authored Sep 14, 2021
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Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>
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  3ddeb0a6
02 Sep, 2021 4 commits
- override deepcopy method · 3fa7d127
  aneels3 authored Aug 09, 2021
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Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>
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  3fa7d127
- Fix issue with illegal_instr_testi and randselect · d458a771
  aneels3 authored Jul 22, 2021
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Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>
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  d458a771
- Fixed b_extension_c() issue · a9c08da5
  shrujal20 authored Jul 21, 2021
  
  a9c08da5
- Fixed get_rand_spf_dpf_value() issue · a4618548
  shrujal20 authored Jul 21, 2021
  
  a4618548
17 Aug, 2021 1 commit
- Add support for RV32C coverage · 07f674c6
  aneels3 authored Aug 16, 2021
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Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>
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  07f674c6
05 Aug, 2021 1 commit
- Add README.md for PyFlow · 438ea995
  aneels3 authored Jul 20, 2021
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Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>
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  438ea995
29 Jul, 2021 2 commits
- Merge pull request #811 from saurabhsingh-pvips/gen_timeout · f255eac0
  Hodjat Asghari Esfeden authored Jul 28, 2021
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[Pygen]: Add gen_timeout for PyFlow
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  f255eac0
- Add gen_timeout for PyFlow · 8dba53fe
  aneels3 authored Jul 21, 2021
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Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>
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  8dba53fe
20 Jul, 2021 5 commits
- Issue #778 fix, change mie behavior in setup_mmode_reg · 575aa6a7
  Henrik Fegran authored Jul 02, 2021
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Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>
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  575aa6a7
- Fixed wrong length of I, S, B-type immediates causing wrong sign extension for certain instructions · a73e0b84
  Henrik Fegran authored Jul 02, 2021
  
  a73e0b84
- Update riscv_compressed_instr.sv · 391ce418
  AryamanAg authored Jun 27, 2021
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Fixed length of binary for cases C_FSDSP, C_SDSP, C_SQSP, C_SWSP and C_FSWSP from 17 bits to 16 bits.
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  391ce418
- Update var binary of function convert2bin · 5a243f62
  AryamanAg authored Jun 27, 2021
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In function convert2bin for I & R formats and category == CSR, binary was only 31 bits. Made it to 32 bits by changing csr[10:0] to csr[11:0].
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  5a243f62
- Improve status reporting · 3df302e1
  Philipp Wagner authored Jul 14, 2021
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Report job progress like "1/2" and "2/2" instead of "0/2" and "1/2", as
it was done before.

Only a cosmetic change.
Signed-off-by: Philipp Wagner <phw@lowrisc.org>
```
  3df302e1
26 May, 2021 1 commit
- update ml/testlist.yaml to get better coverage · 2b2abda6
  Udi Jonnalagadda authored May 25, 2021
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Signed-off-by: Udi Jonnalagadda <udij@google.com>
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  2b2abda6
28 Apr, 2021 1 commit
- add m extension covgroup · 5a79a54f
  ishita71 authored Apr 13, 2021
  
  5a79a54f
10 Apr, 2021 1 commit
- Update pygen_src files · e1a99df3
  aneels3 authored Mar 24, 2021
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Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>
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  e1a99df3
02 Apr, 2021 1 commit

Update scripts for Metrics CI regression: · 59dcd8c8

Aimee Sutton authored Feb 09, 2021


 bug fixes, change ISS to spike in CI regression
Signed-off-by: Aimee Sutton <aimee.sutton@metrics.ca>

59dcd8c8

24 Mar, 2021 1 commit
- Add illegal and load store instruction · c1ef9953
  aneels3 authored Mar 24, 2021
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Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>
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  c1ef9953
22 Mar, 2021 2 commits
- Avoid generating hint instruction when RV32C is turned off (#787) · 0f95ad7f
  taoliug authored Mar 21, 2021
  
  0f95ad7f
- Fix illegal opcode issue in the cov_test (#786) · a64935f5
  taoliug authored Mar 21, 2021
  
  a64935f5
09 Mar, 2021 1 commit

[questa] Remove -access=rwc from vlog command line arguments · 51ddfc1e

Rupert Swarbrick authored Feb 25, 2021

This doesn't seem to be supported by at least Questa 2020.03 (see
issue #780). I don't have a Questa licence or manual locally, but it
looks like this is an Xcelium flag. Maybe it was supported by other
Questa versions as a compatibility shim? If we need to allow the
equivalent access, I think the argument is "+acc", but I'm not
convinced it's needed at all, so suggest removing it entirely.

51ddfc1e

05 Mar, 2021 1 commit

[ci] temporarily disable CI flow · 0aa8a8f9

Udi Jonnalagadda authored Mar 04, 2021

CI currently fails due to some backend issue,
temporarily disable it on all PRs until a fix
is implemented.

0aa8a8f9

04 Mar, 2021 3 commits
- fix issue with rcs for num_of_harts · 0930aeaa
  aneels3 authored Feb 16, 2021
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Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>
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  0930aeaa
- fix multi-hart label issue · c3789e47
  aneels3 authored Feb 14, 2021
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Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>
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  c3789e47
- add multi_hart test · a236d521
  ishita71 authored Feb 11, 2021
  
  a236d521
23 Feb, 2021 4 commits
- Fix minor issues · 99fb5587
  aneels3 authored Feb 03, 2021
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Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>
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  99fb5587
- Add riscv_signature_pkg · 45016e91
  aneels3 authored Jan 28, 2021
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Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>
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  45016e91
- add gen_signature_handshake · 453c135b
  ishita71 authored Jan 25, 2021
  
  453c135b
- Add gen_interrupt_vector_table · ea82bb2a
  aneels3 authored Jan 25, 2021
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Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>
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  ea82bb2a
18 Feb, 2021 3 commits
- Remove the unnecessary lines · e0fb76a6
  Anil Sharma authored Jan 21, 2021
  
  e0fb76a6
- fix issue with riscv_rand_instr_test · 31b739e8
  aneels3 authored Jan 21, 2021
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Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>
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  31b739e8
- Add multiprocessing code block · 636c03e1
  aneels3 authored Jan 16, 2021
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Signed-off-by: aneels3 <b150023ec@nitsikkim.ac.in>
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  636c03e1
14 Jan, 2021 1 commit
- Merge pull request #743 from aimeepsutton/master · 0b625258
  udinator authored Jan 13, 2021
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Add scripts to integrate with Metrics regression platform
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  0b625258
09 Jan, 2021 2 commits
- Add a knob to use rounding mode from the instruction (#767) · c95197e8
  taoliug authored Jan 08, 2021
  
  c95197e8
- Add rounding mode support for floating point arithmetic instructions (#766) · 39b403b8
  taoliug authored Jan 08, 2021
  
  39b403b8