Unverified Commit adfe6f77 authored by Hodjat Asghari Esfeden's avatar Hodjat Asghari Esfeden Committed by GitHub
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Merge pull request #815 from saurabhsingh-pvips/rv32c_cov

[Pygen]: Add coverage for RV32C instruction
parents 3fa7d127 3ddeb0a6
......@@ -19,11 +19,11 @@ import vsc
import logging
from importlib import import_module
from enum import Enum, IntEnum, auto
from bitstring import BitArray
from pygen_src.riscv_instr_pkg import *
from pygen_src.riscv_instr_gen_config import cfg
rcs = import_module("pygen_src.target." + cfg.argv.target + ".riscv_core_setting")
class operand_sign_e(IntEnum):
POSITIVE = 0
NEGATIVE = auto()
......@@ -325,10 +325,11 @@ class riscv_cov_instr:
the result of the check_hazard_condition won't be accurate. Need to
explicitly extract the destination register from the operands '''
if pre_instr.has_rd:
if ((self.has_rs1 and self.rs1 == pre_instr.rd) or
(self.has_rs2 and self.rs1 == pre_instr.rd)):
if ((self.has_rs1 and (self.rs1 == pre_instr.rd)) or
(self.has_rs2 and (self.rs1 == pre_instr.rd))):
logging.info("pre_instr {}".format(pre_instr.instr.name))
self.gpr_hazard = hazard_e["RAW_HAZARD"]
elif self.has_rd and self.rd == pre_instr.rd:
elif self.has_rd and (self.rd == pre_instr.rd):
self.gpr_hazard = hazard_e["WAW_HAZARD"]
elif (self.has_rd and
((pre_instr.has_rs1 and (pre_instr.rs1 == self.rd)) or
......@@ -338,16 +339,16 @@ class riscv_cov_instr:
self.gpr_hazard = hazard_e["NO_HAZARD"]
if self.category == riscv_instr_category_t.LOAD:
if (pre_instr.category == riscv_instr_category_t.STORE and
pre_instr.mem_addr.get_val() == self.mem_addr.get_val()):
(pre_instr.mem_addr.get_val() == self.mem_addr.get_val())):
self.lsu_hazard = hazard_e["RAW_HAZARD"]
else:
self.lsu_hazard = hazard_e["NO_HAZARD"]
if self.category == riscv_instr_category_t.STORE:
if (pre_instr.category == riscv_instr_category_t.STORE and
pre_instr.mem_addr.get_val() == self.mem_addr.get_val()):
(pre_instr.mem_addr.get_val() == self.mem_addr.get_val())):
self.lsu_hazard = hazard_e["WAW_HAZARD"]
elif (pre_instr.category == riscv_instr_category_t.LOAD and
pre_instr.mem_addr.get_val() == self.mem_addr.get_val()):
(pre_instr.mem_addr.get_val() == self.mem_addr.get_val())):
self.lsu_hazard = hazard_e["WAR_HAZARD"]
else:
self.lsu_hazard = hazard_e["NO_HAZARD"]
......
This diff is collapsed.
......@@ -1175,42 +1175,6 @@ class jalr_riscv_reg_t(IntEnum):
RA = 0
T1 = auto()
# Ignore ZERO as src1 of load instructions
class riscv_reg_ex_zero_t(IntEnum):
RA = 0
SP = auto()
GP = auto()
TP = auto()
T0 = auto()
T1 = auto()
T2 = auto()
S0 = auto()
S1 = auto()
A0 = auto()
A1 = auto()
A2 = auto()
A3 = auto()
A4 = auto()
A5 = auto()
A6 = auto()
A7 = auto()
S2 = auto()
S3 = auto()
S4 = auto()
S5 = auto()
S6 = auto()
S7 = auto()
S8 = auto()
S9 = auto()
S10 = auto()
S11 = auto()
T3 = auto()
T4 = auto()
T5 = auto()
T6 = auto()
# PMP address matching mode
class pmp_addr_mode_t(Enum):
OFF = 0b00
......@@ -1282,8 +1246,8 @@ class all_gpr(Enum):
T6 = auto()
class compressed_gpr(Enum):
S0 = 0
class compressed_gpr(IntEnum):
S0 = 8
S1 = auto()
A0 = auto()
A1 = auto()
......@@ -1293,7 +1257,7 @@ class compressed_gpr(Enum):
A5 = auto()
class all_categories(Enum):
class all_categories(IntEnum):
LOAD = 0
STORE = auto()
SHIFT = auto()
......@@ -1311,6 +1275,75 @@ class all_categories(Enum):
INTERRUPT = auto()
AMO = auto()
# Ignore ZERO and SP
class riscv_reg_ex_zero_sp_t(IntEnum):
RA = 1
GP = 3
TP = auto()
T0 = auto()
T1 = auto()
T2 = auto()
S0 = auto()
S1 = auto()
A0 = auto()
A1 = auto()
A2 = auto()
A3 = auto()
A4 = auto()
A5 = auto()
A6 = auto()
A7 = auto()
S2 = auto()
S3 = auto()
S4 = auto()
S5 = auto()
S6 = auto()
S7 = auto()
S8 = auto()
S9 = auto()
S10 = auto()
S11 = auto()
T3 = auto()
T4 = auto()
T5 = auto()
T6 = auto()
# Ignore ZERO only
class riscv_reg_ex_zero_t(IntEnum):
RA = 1
SP = auto()
GP = auto()
TP = auto()
T0 = auto()
T1 = auto()
T2 = auto()
S0 = auto()
S1 = auto()
A0 = auto()
A1 = auto()
A2 = auto()
A3 = auto()
A4 = auto()
A5 = auto()
A6 = auto()
A7 = auto()
S2 = auto()
S3 = auto()
S4 = auto()
S5 = auto()
S6 = auto()
S7 = auto()
S8 = auto()
S9 = auto()
S10 = auto()
S11 = auto()
T3 = auto()
T4 = auto()
T5 = auto()
T6 = auto()
# Currently PyVSC doesn't supports ignore bins
# TODO riscv_reg_ex_zero_sp_t and riscv_reg_ex_zero_t is added as a WA and it can be removed later.
def get_val(in_string, hexa=0):
if len(in_string) > 2:
......@@ -1525,6 +1558,88 @@ def get_attr_list(instr_name):
riscv_instr_name_t.REMU: [riscv_instr_format_t.R_FORMAT,
riscv_instr_category_t.ARITHMETIC,
riscv_instr_group_t.RV32M],
# RV32C
riscv_instr_name_t.C_LW: [riscv_instr_format_t.CL_FORMAT,
riscv_instr_category_t.LOAD,
riscv_instr_group_t.RV32C, imm_t.UIMM],
riscv_instr_name_t.C_SW: [riscv_instr_format_t.CS_FORMAT,
riscv_instr_category_t.STORE,
riscv_instr_group_t.RV32C, imm_t.UIMM],
riscv_instr_name_t.C_LWSP: [riscv_instr_format_t.CI_FORMAT,
riscv_instr_category_t.LOAD,
riscv_instr_group_t.RV32C, imm_t.UIMM],
riscv_instr_name_t.C_SWSP: [riscv_instr_format_t.CSS_FORMAT,
riscv_instr_category_t.STORE,
riscv_instr_group_t.RV32C, imm_t.UIMM],
riscv_instr_name_t.C_ADDI4SPN: [riscv_instr_format_t.CIW_FORMAT,
riscv_instr_category_t.ARITHMETIC,
riscv_instr_group_t.RV32C, imm_t.NZUIMM],
riscv_instr_name_t.C_ADDI: [riscv_instr_format_t.CI_FORMAT,
riscv_instr_category_t.ARITHMETIC,
riscv_instr_group_t.RV32C, imm_t.NZIMM],
riscv_instr_name_t.C_ADDI16SP: [riscv_instr_format_t.CI_FORMAT,
riscv_instr_category_t.ARITHMETIC,
riscv_instr_group_t.RV32C, imm_t.NZIMM],
riscv_instr_name_t.C_LI: [riscv_instr_format_t.CI_FORMAT,
riscv_instr_category_t.ARITHMETIC,
riscv_instr_group_t.RV32C],
riscv_instr_name_t.C_LUI: [riscv_instr_format_t.CI_FORMAT,
riscv_instr_category_t.ARITHMETIC,
riscv_instr_group_t.RV32C, imm_t.NZIMM],
riscv_instr_name_t.C_SUB: [riscv_instr_format_t.CA_FORMAT,
riscv_instr_category_t.ARITHMETIC,
riscv_instr_group_t.RV32C],
riscv_instr_name_t.C_ADD: [riscv_instr_format_t.CR_FORMAT,
riscv_instr_category_t.ARITHMETIC,
riscv_instr_group_t.RV32C],
riscv_instr_name_t.C_NOP: [riscv_instr_format_t.CI_FORMAT,
riscv_instr_category_t.ARITHMETIC,
riscv_instr_group_t.RV32C],
riscv_instr_name_t.C_MV: [riscv_instr_format_t.CR_FORMAT,
riscv_instr_category_t.ARITHMETIC,
riscv_instr_group_t.RV32C],
riscv_instr_name_t.C_ANDI: [riscv_instr_format_t.CB_FORMAT,
riscv_instr_category_t.LOGICAL,
riscv_instr_group_t.RV32C],
riscv_instr_name_t.C_XOR: [riscv_instr_format_t.CA_FORMAT,
riscv_instr_category_t.LOGICAL,
riscv_instr_group_t.RV32C],
riscv_instr_name_t.C_OR: [riscv_instr_format_t.CA_FORMAT,
riscv_instr_category_t.LOGICAL,
riscv_instr_group_t.RV32C],
riscv_instr_name_t.C_AND: [riscv_instr_format_t.CA_FORMAT,
riscv_instr_category_t.LOGICAL,
riscv_instr_group_t.RV32C],
riscv_instr_name_t.C_BEQZ: [riscv_instr_format_t.CB_FORMAT,
riscv_instr_category_t.BRANCH,
riscv_instr_group_t.RV32C],
riscv_instr_name_t.C_BNEZ: [riscv_instr_format_t.CB_FORMAT,
riscv_instr_category_t.BRANCH,
riscv_instr_group_t.RV32C],
riscv_instr_name_t.C_SRLI: [riscv_instr_format_t.CB_FORMAT,
riscv_instr_category_t.SHIFT,
riscv_instr_group_t.RV32C, imm_t.NZUIMM],
riscv_instr_name_t.C_SRAI: [riscv_instr_format_t.CB_FORMAT,
riscv_instr_category_t.SHIFT,
riscv_instr_group_t.RV32C, imm_t.NZUIMM],
riscv_instr_name_t.C_SLLI: [riscv_instr_format_t.CI_FORMAT,
riscv_instr_category_t.SHIFT,
riscv_instr_group_t.RV32C, imm_t.NZUIMM],
riscv_instr_name_t.C_J: [riscv_instr_format_t.CJ_FORMAT,
riscv_instr_category_t.JUMP,
riscv_instr_group_t.RV32C],
riscv_instr_name_t.C_JAL: [riscv_instr_format_t.CJ_FORMAT,
riscv_instr_category_t.JUMP,
riscv_instr_group_t.RV32C],
riscv_instr_name_t.C_JR: [riscv_instr_format_t.CR_FORMAT,
riscv_instr_category_t.JUMP,
riscv_instr_group_t.RV32C],
riscv_instr_name_t.C_JALR: [riscv_instr_format_t.CR_FORMAT,
riscv_instr_category_t.JUMP,
riscv_instr_group_t.RV32C],
riscv_instr_name_t.C_EBREAK: [riscv_instr_format_t.CI_FORMAT,
riscv_instr_category_t.SYSTEM,
riscv_instr_group_t.RV32C],
}
# if instruction is not present in the dictionary,second argument well
# be assigned as default value of passed argument
......
......@@ -106,6 +106,11 @@ class riscv_instr_cov_test:
def get_coverage_report(self):
model = vsc.get_coverage_report_model()
cov_dir = cfg.argv.log_file_name.split("/")[0]
file = open('{}/CoverageGroups.txt'.format(cov_dir), 'w')
file.write("CoverGroups, CoverPoints and Bins Summary\n")
str_report = vsc.get_coverage_report(details=True)
file.write("{}\n".format(str_report))
file.close()
file = open('{}/CoverageReport.txt'.format(cov_dir), 'w')
file.write("Groups Coverage Summary\n")
file.write("Total groups in report: {}\n".format(
......@@ -125,18 +130,6 @@ class riscv_instr_cov_test:
pass
def sample(self):
binary = vsc.int_t(rcs.XLEN)
binary.set_val(get_val(self.trace["binary"], hexa=1))
# TODO: Currently handled using string formatting as part select
# isn't yet supported for global vsc variables
# width is rcs.XLEN+2 because of 0b in the beginning of binary_bin
binary_bin = format(binary.get_val(), '#0{}b'.format(rcs.XLEN + 2))
if binary_bin[-2:] != "11": # TODO: and RV32C in supported_isa
# TODO: sample compressed instruction
pass
if binary_bin[-2:] == "11":
# TODO: sampling
pass
processed_instr_name = self.process_instr_name(self.trace["instr"])
if processed_instr_name in riscv_instr_name_t.__members__:
instr_name = riscv_instr_name_t[processed_instr_name]
......@@ -145,9 +138,10 @@ class riscv_instr_cov_test:
# cov_instr is created, time to manually assign attributes
# TODO: This will get fixed later when we get an inst from template
instruction.assign_attributes()
if instruction.group.name in ["RV32I", "RV32M", "RV32C", "RV64I",
if (instruction.group.name in ["RV32I", "RV32M", "RV32C", "RV64I",
"RV64M", "RV64C", "RV32F", "RV64F",
"RV32D", "RV64D", "RV32B", "RV64B"]:
"RV32D", "RV64D", "RV32B", "RV64B"]) \
and (instruction.group in rcs.supported_isa):
self.assign_trace_info_to_instr(instruction)
instruction.pre_sample()
self.instr_cg.sample(instruction)
......@@ -178,7 +172,7 @@ class riscv_instr_cov_test:
def process_instr_name(self, instruction):
instruction = instruction.upper()
instruction.replace(".", "_")
instruction = instruction.replace(".", "_")
instruction = self.update_instr_name(instruction)
return instruction
......
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