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Panda
RISC-V DV
Commits
3f584ade
Unverified
Commit
3f584ade
authored
Mar 09, 2020
by
udinator
Committed by
GitHub
Mar 09, 2020
Browse files
Merge pull request #510 from udinator/pmp
update ebreak generation for ML test
parents
6344e951
18c3a345
Changes
1
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Side-by-side
test/riscv_instr_test_lib.sv
View file @
3f584ade
...
...
@@ -48,13 +48,12 @@ class riscv_ml_test extends riscv_instr_base_test;
virtual
function
void
randomize_cfg
();
cfg
.
no_fence
=
0
;
cfg
.
no_ebreak
=
0
;
cfg
.
init_privileged_mode
=
MACHINE_MODE
;
cfg
.
init_privileged_mode
.
rand_mode
(
0
);
cfg
.
enable_unaligned_load_store
=
1'b1
;
cfg
.
addr_translaction_rnd_order_c
.
constraint_mode
(
0
);
`DV_CHECK_RANDOMIZE_FATAL
(
cfg
)
cfg
.
addr_translaction_rnd_order_c
.
constraint_mode
(
1
);
cfg
.
addr_translaction_rnd_order_c
.
constraint_mode
(
1
);
`uvm_info
(
`gfn
,
$
sformatf
(
"riscv_instr_gen_config is randomized:
\n
%0s"
,
cfg
.
sprint
()),
UVM_LOW
)
endfunction
...
...
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