diff --git a/llvm/lib/Target/LoongArch/LoongArch.td b/llvm/lib/Target/LoongArch/LoongArch.td
index 3a211bd3d3245f1e3821e797dbe17a70f4fd0c85..bf465c27ef99c8c94eaf2ad71670f0dc969faa30 100644
--- a/llvm/lib/Target/LoongArch/LoongArch.td
+++ b/llvm/lib/Target/LoongArch/LoongArch.td
@@ -30,27 +30,32 @@ defvar LA32 = DefaultMode;
def LA64 : HwMode<"+64bit">;
// Single Precision floating point
-def FeatureBasicF : SubtargetFeature<"f", "HasBasicF", "true",
- "'F' (Single-Precision Floating-Point)">;
-def HasBasicF : Predicate<"Subtarget->hasBasicF()">,
- AssemblerPredicate<(all_of FeatureBasicF),
- "'F' (Single-Precision Floating-Point)">;
+def FeatureBasicF
+ : SubtargetFeature<"f", "HasBasicF", "true",
+ "'F' (Single-Precision Floating-Point)">;
+def HasBasicF
+ : Predicate<"Subtarget->hasBasicF()">,
+ AssemblerPredicate<(all_of FeatureBasicF),
+ "'F' (Single-Precision Floating-Point)">;
// Double Precision floating point
-def FeatureBasicD : SubtargetFeature<"d", "HasBasicD", "true",
- "'D' (Double-Precision Floating-Point)",
- [FeatureBasicF]>;
-def HasBasicD : Predicate<"Subtarget->hasBasicD()">,
- AssemblerPredicate<(all_of FeatureBasicD),
- "'D' (Double-Precision Floating-Point)">;
+def FeatureBasicD
+ : SubtargetFeature<"d", "HasBasicD", "true",
+ "'D' (Double-Precision Floating-Point)",
+ [FeatureBasicF]>;
+def HasBasicD
+ : Predicate<"Subtarget->hasBasicD()">,
+ AssemblerPredicate<(all_of FeatureBasicD),
+ "'D' (Double-Precision Floating-Point)">;
// Loongson SIMD eXtension (LSX)
def FeatureExtLSX
: SubtargetFeature<"lsx", "HasExtLSX", "true",
"'LSX' (Loongson SIMD Extension)", [FeatureBasicD]>;
-def HasExtLSX : Predicate<"Subtarget->hasExtLSX()">,
- AssemblerPredicate<(all_of FeatureExtLSX),
- "'LSX' (Loongson SIMD Extension)">;
+def HasExtLSX
+ : Predicate<"Subtarget->hasExtLSX()">,
+ AssemblerPredicate<(all_of FeatureExtLSX),
+ "'LSX' (Loongson SIMD Extension)">;
// Loongson Advanced SIMD eXtension (LASX)
def FeatureExtLASX
@@ -66,9 +71,10 @@ def HasExtLASX
def FeatureExtLVZ
: SubtargetFeature<"lvz", "HasExtLVZ", "true",
"'LVZ' (Loongson Virtualization Extension)">;
-def HasExtLVZ : Predicate<"Subtarget->hasExtLVZ()">,
- AssemblerPredicate<(all_of FeatureExtLVZ),
- "'LVZ' (Loongson Virtualization Extension)">;
+def HasExtLVZ
+ : Predicate<"Subtarget->hasExtLVZ()">,
+ AssemblerPredicate<(all_of FeatureExtLVZ),
+ "'LVZ' (Loongson Virtualization Extension)">;
// Loongson Binary Translation (LBT)
def FeatureExtLBT
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td b/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
index 250fc459d1ab9c7ce6403dca5b0e3cdf5dda3188..7c01776646e90f8e7f3a183c1f1274136951eba3 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
@@ -43,7 +43,8 @@ class Pseudo<dag outs, dag ins, list<dag> pattern = [], string asmstr = "">
// 2R-type
// <opcode | rj | rd>
class Fmt2R<bits<22> op, dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<5> rj;
bits<5> rd;
@@ -56,7 +57,8 @@ class Fmt2R<bits<22> op, dag outs, dag ins, string asmstr,
// <opcode | rk | rj | rd>
// <opcode | fk | fj | fd>
class Fmt3R<bits<17> op, dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<5> rk;
bits<5> rj;
bits<5> rd;
@@ -68,7 +70,8 @@ class Fmt3R<bits<17> op, dag outs, dag ins, string asmstr,
}
class Fmt3FR<bits<17> op, dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<5> fk;
bits<5> fj;
bits<5> fd;
@@ -82,7 +85,8 @@ class Fmt3FR<bits<17> op, dag outs, dag ins, string asmstr,
// 4R-type
// <opcode | ra | rk | rj | rd>
class Fmt4R<bits<12> op, dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<5> ra;
bits<5> rk;
bits<5> rj;
@@ -98,7 +102,8 @@ class Fmt4R<bits<12> op, dag outs, dag ins, string asmstr,
// 3RI2-type
// <opcode | I2 | rk | rj | rd>
class Fmt3RI2<bits<15> op, dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<2> imm2;
bits<5> rk;
bits<5> rj;
@@ -114,7 +119,8 @@ class Fmt3RI2<bits<15> op, dag outs, dag ins, string asmstr,
// 3RI3-type
// <opcode | I3 | rk | rj | rd>
class Fmt3RI3<bits<14> op, dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<3> imm3;
bits<5> rk;
bits<5> rj;
@@ -130,7 +136,8 @@ class Fmt3RI3<bits<14> op, dag outs, dag ins, string asmstr,
// 2RI5-type
// <opcode | I5 | rj | rd>
class Fmt2RI5<bits<17> op, dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<5> imm5;
bits<5> rj;
bits<5> rd;
@@ -144,7 +151,8 @@ class Fmt2RI5<bits<17> op, dag outs, dag ins, string asmstr,
// 2RI6-type
// <opcode | I6 | rj | rd>
class Fmt2RI6<bits<16> op, dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<6> imm6;
bits<5> rj;
bits<5> rd;
@@ -158,7 +166,8 @@ class Fmt2RI6<bits<16> op, dag outs, dag ins, string asmstr,
// 2RI8-type
// <opcode | I8 | rj | rd>
class Fmt2RI8<bits<14> op, dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<8> imm8;
bits<5> rj;
bits<5> rd;
@@ -172,7 +181,8 @@ class Fmt2RI8<bits<14> op, dag outs, dag ins, string asmstr,
// 2RI12-type
// <opcode | I12 | rj | rd>
class Fmt2RI12<bits<10> op, dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<12> imm12;
bits<5> rj;
bits<5> rd;
@@ -186,7 +196,8 @@ class Fmt2RI12<bits<10> op, dag outs, dag ins, string asmstr,
// 2RI14-type
// <opcode | I14 | rj | rd>
class Fmt2RI14<bits<8> op, dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<14> imm14;
bits<5> rj;
bits<5> rd;
@@ -200,7 +211,8 @@ class Fmt2RI14<bits<8> op, dag outs, dag ins, string asmstr,
// 2RI16-type
// <opcode | I16 | rj | rd>
class Fmt2RI16<bits<6> op, dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<16> imm16;
bits<5> rj;
bits<5> rd;
@@ -214,7 +226,8 @@ class Fmt2RI16<bits<6> op, dag outs, dag ins, string asmstr,
// 1RI20-type
// <opcode | I20 | rd>
class Fmt1RI20<bits<7> op, dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<20> imm20;
bits<5> rd;
@@ -226,7 +239,8 @@ class Fmt1RI20<bits<7> op, dag outs, dag ins, string asmstr,
// 1RI21-type
// <opcode | I21[15:0] | rj | I21[20:16]>
class Fmt1RI21<bits<6> op, dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<21> imm21;
bits<5> rj;
@@ -239,7 +253,8 @@ class Fmt1RI21<bits<6> op, dag outs, dag ins, string asmstr,
// I15-type
// <opcode | I15>
class FmtI15<bits<17> op, dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<15> imm15;
let Inst{31-15} = op;
@@ -249,7 +264,8 @@ class FmtI15<bits<17> op, dag outs, dag ins, string asmstr,
// I26-type
// <opcode | I26[15:0] | I26[25:16]>
class FmtI26<bits<6> op, dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<26> imm26;
let Inst{31-26} = op;
@@ -260,7 +276,8 @@ class FmtI26<bits<6> op, dag outs, dag ins, string asmstr,
// FmtBSTR_W
// <opcode[11:1] | msbw | opcode[0] | lsbw | rj | rd>
class FmtBSTR_W<bits<12> op, dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<5> msbw;
bits<5> lsbw;
bits<5> rj;
@@ -277,7 +294,8 @@ class FmtBSTR_W<bits<12> op, dag outs, dag ins, string asmstr,
// FmtBSTR_D
// <opcode | msbd | lsbd | rj | rd>
class FmtBSTR_D<bits<10> op, dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<6> msbd;
bits<6> lsbd;
bits<5> rj;
@@ -293,7 +311,8 @@ class FmtBSTR_D<bits<10> op, dag outs, dag ins, string asmstr,
// FmtASRT
// <opcode | rk | rj | 0x0>
class FmtASRT<bits<17> op, dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<5> rk;
bits<5> rj;
@@ -306,7 +325,8 @@ class FmtASRT<bits<17> op, dag outs, dag ins, string asmstr,
// FmtPRELD
// < 0b0010101011 | I12 | rj | I5>
class FmtPRELD<dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<12> imm12;
bits<5> rj;
bits<5> imm5;
@@ -320,7 +340,8 @@ class FmtPRELD<dag outs, dag ins, string asmstr,
// FmtPRELDX
// < 0b00111000001011000 | rk | rj | I5>
class FmtPRELDX<dag outs, dag ins, string asmstr,
- list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
+ list<dag> pattern = []>
+ : LAInst<outs, ins, asmstr, pattern> {
bits<5> rk;
bits<5> rj;
bits<5> imm5;
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
index 7f839f22459a7cca9d5f570ec94e9312512c5307..755e4389d839e849fb37d1ad800510edda7422a6 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
@@ -22,7 +22,8 @@ def loongarch_ret : SDNode<"LoongArchISD::RET", SDTNone,
//===----------------------------------------------------------------------===//
// Operand and SDNode transformation definitions.
//===----------------------------------------------------------------------===//
-class ImmAsmOperand<string prefix, int width, string suffix> : AsmOperandClass {
+class ImmAsmOperand<string prefix, int width, string suffix>
+ : AsmOperandClass {
let Name = prefix # "Imm" # width # suffix;
let DiagnosticType = !strconcat("Invalid", Name);
let RenderMethod = "addImmOperands";
diff --git a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
index 41bef68e61fb31b94c17b41c68ba6e45183300c5..d55b94bcb4240b8a1b9d7f51488cb50079096a83 100644
--- a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
@@ -24,7 +24,8 @@ class LoongArchReg32<bits<16> Enc, string n, list<string> alt = []>
}
def sub_32 : SubRegIndex<32>;
-class LoongArchReg64<LoongArchReg32 subreg> : Register<""> {
+class LoongArchReg64<LoongArchReg32 subreg>
+ : Register<""> {
let HWEncoding = subreg.HWEncoding;
let SubRegs = [subreg];
let SubRegIndices = [sub_32];