Commit 4573236c authored by Minaduki Shigure's avatar Minaduki Shigure
Browse files

Debug 2.0

binary file created.
parent d37c5430
......@@ -61,15 +61,103 @@ proc step_failed { step } {
}
start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
create_project -in_memory -part xc7a35tcpg236-1
set_property design_mode GateLvl [current_fileset]
set_param project.singleFileAddWarning.threshold 0
set_property webtalk.parent_dir {D:/Vivado Projects/Winter_Proj/Winter_Proj.cache/wt} [current_project]
set_property parent.project_path {D:/Vivado Projects/Winter_Proj/Winter_Proj.xpr} [current_project]
set_property ip_output_repo {{D:/Vivado Projects/Winter_Proj/Winter_Proj.cache/ip}} [current_project]
set_property ip_cache_permissions {read write} [current_project]
set_property XPM_LIBRARIES XPM_CDC [current_project]
add_files -quiet {{D:/Vivado Projects/Winter_Proj/Winter_Proj.runs/synth_1/top.dcp}}
read_ip -quiet {{D:/Vivado Projects/Winter_Proj/Winter_Proj.srcs/sources_1/ip/clk_pll/clk_pll.xci}}
read_xdc {{D:/Vivado Projects/Winter_Proj/Winter_Proj.srcs/constrs_1/new/xdcii.xdc}}
link_design -top top -part xc7a35tcpg236-1
close_msg_db -file init_design.pb
} RESULT]
if {$rc} {
step_failed init_design
return -code error $RESULT
} else {
end_step init_design
unset ACTIVE_STEP
}
start_step opt_design
set ACTIVE_STEP opt_design
set rc [catch {
create_msg_db opt_design.pb
opt_design
write_checkpoint -force top_opt.dcp
create_report "impl_1_opt_report_drc_0" "report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx"
close_msg_db -file opt_design.pb
} RESULT]
if {$rc} {
step_failed opt_design
return -code error $RESULT
} else {
end_step opt_design
unset ACTIVE_STEP
}
start_step place_design
set ACTIVE_STEP place_design
set rc [catch {
create_msg_db place_design.pb
if { [llength [get_debug_cores -quiet] ] > 0 } {
implement_debug_core
}
place_design
write_checkpoint -force top_placed.dcp
create_report "impl_1_place_report_io_0" "report_io -file top_io_placed.rpt"
create_report "impl_1_place_report_utilization_0" "report_utilization -file top_utilization_placed.rpt -pb top_utilization_placed.pb"
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file top_control_sets_placed.rpt"
close_msg_db -file place_design.pb
} RESULT]
if {$rc} {
step_failed place_design
return -code error $RESULT
} else {
end_step place_design
unset ACTIVE_STEP
}
start_step route_design
set ACTIVE_STEP route_design
set rc [catch {
create_msg_db route_design.pb
route_design
write_checkpoint -force top_routed.dcp
create_report "impl_1_route_report_drc_0" "report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx"
create_report "impl_1_route_report_methodology_0" "report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx"
create_report "impl_1_route_report_power_0" "report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx"
create_report "impl_1_route_report_route_status_0" "report_route_status -file top_route_status.rpt -pb top_route_status.pb"
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file top_timing_summary_routed.rpt -pb top_timing_summary_routed.pb -rpx top_timing_summary_routed.rpx -warn_on_violation "
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file top_incremental_reuse_routed.rpt"
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file top_clock_utilization_routed.rpt"
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpx"
close_msg_db -file route_design.pb
} RESULT]
if {$rc} {
write_checkpoint -force top_routed_error.dcp
step_failed route_design
return -code error $RESULT
} else {
end_step route_design
unset ACTIVE_STEP
}
start_step write_bitstream
set ACTIVE_STEP write_bitstream
set rc [catch {
create_msg_db write_bitstream.pb
open_checkpoint top_routed.dcp
set_property webtalk.parent_dir {D:/Vivado Projects/Winter_Proj/Winter_Proj.cache/wt} [current_project]
set_property XPM_LIBRARIES XPM_CDC [current_project]
catch { write_mem_info -force top.mmi }
write_bitstream -force top.bit
write_bitstream -force top.bit -bin_file
catch {write_debug_probes -quiet -force top}
catch {file copy -force top.ltx debug_nets.ltx}
close_msg_db -file write_bitstream.pb
......
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Wed Jan 16 10:41:00 2019
| Date : Wed Jan 16 16:21:28 2019
| Host : Player running 64-bit major release (build 9200)
| Command : report_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpx
| Design : top
......
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Wed Jan 16 10:41:00 2019
| Date : Wed Jan 16 16:21:28 2019
| Host : Player running 64-bit major release (build 9200)
| Command : report_clock_utilization -file top_clock_utilization_routed.rpt
| Design : top
......
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Wed Jan 16 10:40:30 2019
| Date : Wed Jan 16 16:21:01 2019
| Host : Player running 64-bit major release (build 9200)
| Command : report_control_sets -verbose -file top_control_sets_placed.rpt
| Design : top
......@@ -70,31 +70,31 @@ Table of Contents
| clk_generator/inst/CLK_200M | | | 1 | 8 |
| ~sCLK_IBUF_BUFG | | CS_IBUF | 2 | 14 |
| clk_generator/inst/CLK_100M | | | 7 | 26 |
| clk_generator/inst/CLK_200M | duty_fast/cat_in_pos | duty_mid/period_cnt[31]_i_1_n_0 | 8 | 62 |
| clk_generator/inst/CLK_100M | | sp_unit/pre/cnt[31]_i_1__1_n_0 | 8 | 62 |
| clk_generator/inst/CLK_100M | | freq/nolabel_line33/cnt[31]_i_1__0_n_0 | 8 | 62 |
| clk_generator/inst/CLK_100M | | freq/pre/cnt[31]_i_1_n_0 | 8 | 62 |
| clk_generator/inst/CLK_100M | | sp_unit/pre/cnt[31]_i_1__1_n_0 | 8 | 62 |
| clk_generator/inst/CLK_200M | duty_fast/cat_in_pos | duty_slow/period_cnt[31]_i_1__0_n_0 | 8 | 62 |
| clk_generator/inst/CLK_100M | phase_fast/phase_cnt | phase_mid/phase_cnt[31]_i_1_n_0 | 8 | 62 |
| clk_generator/inst/CLK_100M | phase_fast/phase_cnt | phase_slow/phase_cnt[31]_i_1__0_n_0 | 8 | 62 |
| clk_generator/inst/CLK_100M | phase_fast/XOR_out | phase_mid/P_on | 8 | 64 |
| clk_generator/inst/CLK_200M | duty_fast/cat_in_pos | duty_slow/period_cnt[31]_i_1__0_n_0 | 8 | 62 |
| clk_generator/inst/CLK_200M | duty_fast/cat_in_pos | duty_mid/period_cnt[31]_i_1_n_0 | 8 | 62 |
| CLK_10k_BUFG | freq/cnt2/cnt_out[31]_i_1__0_n_0 | | 7 | 64 |
| CLK_10k_BUFG | freq/act/cnt_1 | freq/act/cnt0_0 | 8 | 64 |
| clk_generator/inst/CLK_100M | phase_fast/cat_in_pos | | 6 | 64 |
| clk_generator/inst/CLK_100M | phase_fast/XOR_out | phase_fast/cat_in_pos | 8 | 64 |
| clk_generator/inst/CLK_100M | phase_fast/XOR_out | phase_mid/P_on | 8 | 64 |
| clk_generator/inst/CLK_100M | phase_fast/XOR_out | phase_slow/P_on | 8 | 64 |
| clk_generator/inst/CLK_100M | phase_slow/P_on | | 7 | 64 |
| signal1_IBUF_BUFG | sp_unit/cnt1/cnt_out[31]_i_1__1_n_0 | | 9 | 64 |
| clk_generator/inst/CLK_200M | duty_fast/sel | duty_mid/P_on | 8 | 64 |
| clk_generator/inst/CLK_200M | duty_fast/sel | duty_slow/P_on | 8 | 64 |
| clk_generator/inst/CLK_200M | duty_fast/sel | duty_fast/cat_in_pos | 8 | 64 |
| clk_generator/inst/CLK_200M | duty_fast/syn1 | duty_mid/P_on | 8 | 64 |
| clk_generator/inst/CLK_200M | duty_fast/sel | duty_mid/P_on | 8 | 64 |
| clk_generator/inst/CLK_200M | duty_fast/syn1 | duty_slow/P_on | 8 | 64 |
| clk_generator/inst/CLK_200M | duty_fast/syn1 | duty_fast/cat_in_pos | 8 | 64 |
| CLK_10k_BUFG | freq/act/cnt_1 | freq/act/cnt0_0 | 8 | 64 |
| clk_generator/inst/CLK_200M | duty_fast/syn1 | duty_mid/P_on | 8 | 64 |
| signal_IBUF_BUFG | freq/cnt1/cnt_out[31]_i_1_n_0 | | 8 | 64 |
| signal_IBUF_BUFG | freq/act/cnt | freq/act/cnt0 | 8 | 64 |
| CLK_10k_BUFG | freq/cnt2/cnt_out[31]_i_1__0_n_0 | | 7 | 64 |
| clk_generator/inst/CLK_100M | phase_mid/P_on | | 7 | 64 |
| clk_generator/inst/CLK_100M | phase_fast/cat_in_pos | | 6 | 64 |
| clk_generator/inst/CLK_100M | phase_slow/P_on | | 7 | 64 |
| signal1_IBUF_BUFG | sp_unit/act/cnt | sp_unit/act/cnt0 | 8 | 64 |
| signal1_IBUF_BUFG | sp_unit/cnt1/cnt_out[31]_i_1__1_n_0 | | 9 | 64 |
| clk_generator/inst/CLK_100M | phase_mid/P_on | | 7 | 64 |
| clk_generator/inst/CLK_200M | duty_fast/sel | duty_slow/P_on | 8 | 64 |
| clk_generator/inst/CLK_100M | spi_slave/snd_buf | | 9 | 70 |
| ~flag_IBUF_BUFG | | | 19 | 76 |
| clk_generator/inst/CLK_200M | duty_fast/cat_in_pos | | 19 | 128 |
......
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Wed Jan 16 10:40:19 2019
| Date : Wed Jan 16 16:20:49 2019
| Host : Player running 64-bit major release (build 9200)
| Command : report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx
| Design : top
......
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Wed Jan 16 10:40:55 2019
| Date : Wed Jan 16 16:21:25 2019
| Host : Player running 64-bit major release (build 9200)
| Command : report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx
| Design : top
......
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Wed Jan 16 10:40:30 2019
| Date : Wed Jan 16 16:21:00 2019
| Host : Player running 64-bit major release (build 9200)
| Command : report_io -file top_io_placed.rpt
| Design : top
......
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Wed Jan 16 10:40:58 2019
| Date : Wed Jan 16 16:21:26 2019
| Host : Player running 64-bit major release (build 9200)
| Command : report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx
| Design : top
......
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Wed Jan 16 10:40:59 2019
| Date : Wed Jan 16 16:21:27 2019
| Host : Player running 64-bit major release (build 9200)
| Command : report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx
| Design : top
......
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Wed Jan 16 10:40:59 2019
| Date : Wed Jan 16 16:21:27 2019
| Host : Player running 64-bit major release (build 9200)
| Command : report_timing_summary -max_paths 10 -file top_timing_summary_routed.rpt -pb top_timing_summary_routed.pb -rpx top_timing_summary_routed.rpx -warn_on_violation
| Design : top
......
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