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Commit 4573236c authored by Minaduki Shigure's avatar Minaduki Shigure
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Debug 2.0 

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Winter_Proj.cache/wt/gui_handlers.wdf
View file @ 4573236c
version:1
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Winter_Proj.cache/wt/java_command_handlers.wdf
View file @ 4573236c
version:1
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Winter_Proj.cache/wt/project.wpc
View file @ 4573236c
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Winter_Proj.cache/wt/webtalk_pa.xml
View file @ 4573236c
......@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Wed Jan 16 10:41:49 2019">
<application name="pa" timeStamp="Wed Jan 16 16:24:42 2019">
<section name="Project Information" visible="false">
<property name="ProjectID" value="1cca0c60a04042c6b8a721da5d49a00f" type="ProjectID"/>
<property name="ProjectIteration" value="11" type="ProjectIteration"/>
<property name="ProjectIteration" value="12" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
......@@ -17,44 +17,82 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="CloseDesign" value="1" type="JavaHandler"/>
<property name="AddCfgMem" value="1" type="JavaHandler"/>
<property name="AutoConnectTarget" value="2" type="JavaHandler"/>
<property name="CloseDesign" value="2" type="JavaHandler"/>
<property name="ConfigureBitstream" value="1" type="JavaHandler"/>
<property name="CoreView" value="1" type="JavaHandler"/>
<property name="CustomizeCore" value="1" type="JavaHandler"/>
<property name="EditDelete" value="1" type="JavaHandler"/>
<property name="LaunchProgramFpga" value="3" type="JavaHandler"/>
<property name="OpenHardwareManager" value="2" type="JavaHandler"/>
<property name="ProgramCfgMem" value="1" type="JavaHandler"/>
<property name="RecustomizeCore" value="2" type="JavaHandler"/>
<property name="ReportTimingSummary" value="1" type="JavaHandler"/>
<property name="RunBitgen" value="1" type="JavaHandler"/>
<property name="RunBitgen" value="2" type="JavaHandler"/>
<property name="RunImplementation" value="11" type="JavaHandler"/>
<property name="SaveDesign" value="1" type="JavaHandler"/>
<property name="SaveDesign" value="2" type="JavaHandler"/>
<property name="ShowView" value="6" type="JavaHandler"/>
<property name="ToolsSettings" value="2" type="JavaHandler"/>
<property name="ViewTaskImplementation" value="2" type="JavaHandler"/>
<property name="ViewTaskSynthesis" value="1" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="AbstractFileView_RELOAD" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_APPLY" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="29" type="GuiHandlerData"/>
<property name="BaseDialog_YES" value="6" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="39" type="GuiHandlerData"/>
<property name="BaseDialog_YES" value="7" type="GuiHandlerData"/>
<property name="CfgMemPartChooser_TABLE" value="1" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="5" type="GuiHandlerData"/>
<property name="ConfigureBitstreamDialog_TOC_LIST" value="2" type="GuiHandlerData"/>
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="3" type="GuiHandlerData"/>
<property name="CreateConstraintsFilePanel_FILE_NAME" value="1" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="23" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="18" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="25" type="GuiHandlerData"/>
<property name="HJFileChooserRecentListPreview_RECENT_DIRECTORIES" value="1" type="GuiHandlerData"/>
<property name="HardwareTreePanel_HARDWARE_TREE_TABLE" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_EDIT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_FLOORPLANNING" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_IO_PLANNING" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_TIMING" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_TOOLS" value="4" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_SEVERITY" value="1" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="61" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="62" type="GuiHandlerData"/>
<property name="MsgView_INFORMATION_MESSAGES" value="2" type="GuiHandlerData"/>
<property name="MsgView_WARNING_MESSAGES" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_CONFIG_MEMORY" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_IMPL_DESIGN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_NETLIST_DESIGN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_CONFIG_BITSTREAM" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_HARDWARE_MANAGER" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_BITGEN" value="1" type="GuiHandlerData"/>
<property name="ProgramCfgMemDialog_CONTENTS_OF_CONFIGURATION_FILE" value="4" type="GuiHandlerData"/>
<property name="ProgramDebugTab_OPEN_TARGET" value="2" type="GuiHandlerData"/>
<property name="ProgramDebugTab_PROGRAM_DEVICE" value="3" type="GuiHandlerData"/>
<property name="ProgramFpgaDialog_PROGRAM" value="3" type="GuiHandlerData"/>
<property name="ProjectSettingsGadget_EDIT_PROJECT_SETTINGS" value="2" type="GuiHandlerData"/>
<property name="RDICommands_CUSTOM_COMMANDS" value="9" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
<property name="RemoveSourcesDialog_ALSO_DELETE" value="1" type="GuiHandlerData"/>
<property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/>
<property name="SaveProjectUtils_SAVE" value="1" type="GuiHandlerData"/>
<property name="SettingsDialog_PROJECT_TREE" value="1" type="GuiHandlerData"/>
<property name="SignalTreePanel_SIGNAL_TREE_TABLE" value="29" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="2" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_SYNTHESIZE_DESIGN_GLOBALLY" value="1" type="GuiHandlerData"/>
<property name="SrcMenu_IP_DOCUMENTATION" value="2" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="4" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="2" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="3" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="15" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="10" type="TclMode"/>
</item>
</section>
</application>
......
Winter_Proj.hw/hw_1/hw.xml
View file @ 4573236c
......@@ -5,11 +5,25 @@
<hwsession version="1" minor="2">
<device name="xc7a35t_0" gui_info=""/>
<ObjectList object_type="hw_cfgmem" gui_info="">
<Object name="" gui_info="">
<Properties Property="PROGRAM.ADDRESS_RANGE" value="use_file"/>
<Properties Property="PROGRAM.BLANK_CHECK" value="0"/>
<Properties Property="PROGRAM.CFG_PROGRAM" value="1"/>
<Properties Property="PROGRAM.CHECKSUM" value="0"/>
<Properties Property="PROGRAM.ERASE" value="1"/>
<Properties Property="PROGRAM.FILES" value="$_project_name_.runs/impl_1/top.bin"/>
<Properties Property="PROGRAM.PRM_FILE" value=""/>
<Properties Property="PROGRAM.UNUSED_PIN_TERMINATION" value="pull-none"/>
<Properties Property="PROGRAM.VERIFY" value="1"/>
</Object>
</ObjectList>
<ObjectList object_type="hw_device" gui_info="">
<Object name="xc7a35t_0" gui_info="">
<Properties Property="FULL_PROBES.FILE" value=""/>
<Properties Property="PROBES.FILE" value=""/>
<Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/top.bit"/>
<Properties Property="PROGRAM.HW_BITSTREAM" value=""/>
<Properties Property="PROGRAM.HW_CFGMEM_PART" value="s25fl032p-spi-x1_x2_x4"/>
<Properties Property="SLR.COUNT" value="1"/>
</Object>
</ObjectList>
......
Winter_Proj.runs/.jobs/vrs_config_11.xml 0 → 100644
View file @ 4573236c
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="D:/Vivado Projects/Winter_Proj/Winter_Proj.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream"/>
</Runs>
Winter_Proj.runs/impl_1/.init_design.begin.rst
View file @ 4573236c
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="wukan" Host="PLAYER" Pid="23024">
<Process Command=".planAhead." Owner="wukan" Host="PLAYER" Pid="23496">
</Process>
</ProcessHandle>
Winter_Proj.runs/impl_1/.opt_design.begin.rst
View file @ 4573236c
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="wukan" Host="PLAYER" Pid="23024">
<Process Command=".planAhead." Owner="wukan" Host="PLAYER" Pid="23496">
</Process>
</ProcessHandle>
Winter_Proj.runs/impl_1/.place_design.begin.rst
View file @ 4573236c
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="wukan" Host="PLAYER" Pid="23024">
<Process Command=".planAhead." Owner="wukan" Host="PLAYER" Pid="23496">
</Process>
</ProcessHandle>
Winter_Proj.runs/impl_1/.route_design.begin.rst
View file @ 4573236c
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="wukan" Host="PLAYER" Pid="23024">
<Process Command=".planAhead." Owner="wukan" Host="PLAYER" Pid="23496">
</Process>
</ProcessHandle>
Winter_Proj.runs/impl_1/.vivado.begin.rst
View file @ 4573236c
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado.bat" Owner="wukan" Host="PLAYER" Pid="23224">
</Process>
</ProcessHandle>
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado.bat" Owner="wukan" Host="PLAYER" Pid="17672">
<Process Command="vivado.bat" Owner="wukan" Host="PLAYER" Pid="24308">
</Process>
</ProcessHandle>
Winter_Proj.runs/impl_1/.write_bitstream.begin.rst
View file @ 4573236c
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="wukan" Host="PLAYER" Pid="19584">
<Process Command=".planAhead." Owner="wukan" Host="PLAYER" Pid="23496">
</Process>
</ProcessHandle>
Winter_Proj.runs/impl_1/gen_run.xml
View file @ 4573236c
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1547606343">
<GenRun Id="impl_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1547626809">
<File Type="BITSTR-BMM" Name="top_bd.bmm"/>
<File Type="OPT-METHODOLOGY-DRC" Name="top_methodology_drc_opted.rpt"/>
<File Type="INIT-TIMING" Name="top_timing_summary_init.rpt"/>
......@@ -133,7 +133,9 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
......@@ -142,6 +144,8 @@
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
<Step Id="write_bitstream">
<Option Id="BinFile">1</Option>
</Step>
</Strategy>
</GenRun>
Winter_Proj.runs/impl_1/rundef.js
View file @ 4573236c
......@@ -23,7 +23,7 @@ eval( EAInclude(ISEJScriptLib) );
// pre-commands:
ISETouchFile( "write_bitstream", "begin" );
ISETouchFile( "init_design", "begin" );
ISEStep( "vivado",
"-log top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace" );
......
Winter_Proj.runs/impl_1/runme.log
View file @ 4573236c
......@@ -22,7 +22,7 @@ Finished Parsing XDC File [d:/Vivado Projects/Winter_Proj/Winter_Proj.srcs/sourc
Parsing XDC File [d:/Vivado Projects/Winter_Proj/Winter_Proj.srcs/sources_1/ip/clk_pll/clk_pll.xdc] for cell 'clk_generator/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/Vivado Projects/Winter_Proj/Winter_Proj.srcs/sources_1/ip/clk_pll/clk_pll.xdc:57]
INFO: [Timing 38-2] Deriving generated clocks [d:/Vivado Projects/Winter_Proj/Winter_Proj.srcs/sources_1/ip/clk_pll/clk_pll.xdc:57]
get_clocks: Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1221.500 ; gain = 563.961
get_clocks: Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1221.184 ; gain = 564.234
Finished Parsing XDC File [d:/Vivado Projects/Winter_Proj/Winter_Proj.srcs/sources_1/ip/clk_pll/clk_pll.xdc] for cell 'clk_generator/inst'
Parsing XDC File [D:/Vivado Projects/Winter_Proj/Winter_Proj.srcs/constrs_1/new/xdcii.xdc]
Finished Parsing XDC File [D:/Vivado Projects/Winter_Proj/Winter_Proj.srcs/constrs_1/new/xdcii.xdc]
......@@ -32,7 +32,7 @@ No Unisim elements were transformed.
9 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1221.500 ; gain = 883.273
link_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1221.184 ; gain = 883.457
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
......@@ -43,13 +43,13 @@ INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.778 . Memory (MB): peak = 1221.500 ; gain = 0.000
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.859 . Memory (MB): peak = 1221.184 ; gain = 0.000
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1ab568f2d
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.079 . Memory (MB): peak = 1237.852 ; gain = 16.352
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.122 . Memory (MB): peak = 1237.738 ; gain = 16.555
Starting Logic Optimization Task
......@@ -58,57 +58,57 @@ INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1ab568f2d
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.103 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.096 . Memory (MB): peak = 1237.738 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 1ab568f2d
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.124 . Memory (MB): peak = 1237.738 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 14942434f
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.175 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.162 . Memory (MB): peak = 1237.738 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 14942434f
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.212 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.204 . Memory (MB): peak = 1237.738 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 23fb34c84
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.328 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.322 . Memory (MB): peak = 1237.738 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 23fb34c84
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.336 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.330 . Memory (MB): peak = 1237.738 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1237.738 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 23fb34c84
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.343 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.338 . Memory (MB): peak = 1237.738 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 23fb34c84
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1237.738 ; gain = 0.000
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 23fb34c84
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1237.738 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
......@@ -117,7 +117,7 @@ Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1237.852 ; gain = 0.000
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.060 . Memory (MB): peak = 1237.738 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'D:/Vivado Projects/Winter_Proj/Winter_Proj.runs/impl_1/top_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx
Command: report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx
......@@ -141,11 +141,11 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1237.852 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1aa5e91be
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1237.852 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1237.738 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
......@@ -171,33 +171,33 @@ WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. T
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 78e333cb
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 7b5a018f
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 7b5a018f
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 7b5a018f
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 147d0cf85
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 2.2 Physical Synthesis In Placer
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1237.852 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1237.738 ; gain = 0.000
Summary of Physical Synthesis Optimizations
============================================
......@@ -213,60 +213,60 @@ Summary of Physical Synthesis Optimizations
Phase 2.2 Physical Synthesis In Placer | Checksum: 7ca1385b
Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 2 Global Placement | Checksum: af42c8d5
Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: af42c8d5
Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 161fbbede
Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1dd17218f
Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1dd17218f
Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 3.5 Timing Path Optimizer
Phase 3.5 Timing Path Optimizer | Checksum: 1dd17218f
Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 3.6 Fast Optimization
Phase 3.6 Fast Optimization | Checksum: 134c1d64b
Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 3.7 Small Shape Detail Placement
Phase 3.7 Small Shape Detail Placement | Checksum: 1d3e73fbf
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 3.8 Re-assign LUT pins
Phase 3.8 Re-assign LUT pins | Checksum: 1ce84c4df
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 3.9 Pipeline Register Optimization
Phase 3.9 Pipeline Register Optimization | Checksum: 1ce84c4df
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 3 Detail Placement | Checksum: 1ce84c4df
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up
......@@ -280,52 +280,52 @@ Phase 4.1.1.1 BUFG Insertion
INFO: [Place 46-31] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
Phase 4.1.1.1 BUFG Insertion | Checksum: 1ce9ec369
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 1237.738 ; gain = 0.000
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.499. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 18d72206a
Time (s): cpu = 00:00:12 ; elapsed = 00:00:09 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 4.1 Post Commit Optimization | Checksum: 18d72206a
Time (s): cpu = 00:00:12 ; elapsed = 00:00:09 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 18d72206a
Time (s): cpu = 00:00:12 ; elapsed = 00:00:09 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 18d72206a
Time (s): cpu = 00:00:12 ; elapsed = 00:00:09 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: 1509424cb
Time (s): cpu = 00:00:12 ; elapsed = 00:00:09 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 1237.738 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1509424cb
Time (s): cpu = 00:00:12 ; elapsed = 00:00:09 . Memory (MB): peak = 1237.852 ; gain = 0.000
Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 1237.738 ; gain = 0.000
Ending Placer Task | Checksum: 6ebe5b54