提交 3a47ab5c 编辑于 作者: Minaduki Shigure's avatar Minaduki Shigure
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Debug 0.0

CLK_200M required.
Method of SPI to be figured out.
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version:1
6d6f64655f636f756e7465727c4755494d6f6465:1
eof:
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2018.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/01/15 14:15:26
// Design Name:
// Module Name: Duty_Counter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Duty_Counter_1(
input CLK,
input cat_in,
output reg [31:0] P_on,
output reg [31:0] P_off
);
reg syn1;
reg syn2;
wire cat_in_pos;
reg [31:0] P_on_reg;
reg [31:0] P_off_reg;
always @ (posedge CLK)
begin
syn1 <= cat_in;
syn2 <= syn1;
end
assign cat_in_pos = syn1 & (~syn2);
always @ (posedge CLK)
begin
if (cat_in_pos)
begin
P_on <= P_on_reg;
P_off <= P_off_reg;
P_on_reg <= 32'b0;
P_off_reg <= 32'b0;
end
else if (syn1)
P_on_reg <= P_on_reg + 1'b1;
else
P_off_reg <= P_off_reg + 1'b1;
end
endmodule
module Duty_Counter_2(
input CLK,
input cat_in,
output reg [31:0] P_on,
output reg [31:0] P_off
);
reg syn1;
reg syn2;
wire cat_in_pos;
reg [31:0] P_on_reg;
reg [31:0] P_off_reg;
reg [31:0] period_cnt;
always @ (posedge CLK)
begin
syn1 <= cat_in;
syn2 <= syn1;
end
assign cat_in_pos = syn1 & (~syn2);
always @ (posedge CLK)
begin
if (cat_in_pos)
period_cnt <= period_cnt + 1'b1;
if (period_cnt == 32'd1000)
begin
P_on <= P_on_reg;
P_off <= P_off_reg;
P_on_reg <= 32'b0;
P_off_reg <= 32'b0;
period_cnt <= 32'b0;
end
else if (syn1)
P_on_reg <= P_on_reg + 1'b1;
else
P_off_reg <= P_off_reg + 1'b1;
end
endmodule
module Duty_Counter_3(
input CLK,
input cat_in,
output reg [31:0] P_on,
output reg [31:0] P_off
);
reg syn1;
reg syn2;
wire cat_in_pos;
reg [31:0] P_on_reg;
reg [31:0] P_off_reg;
reg [31:0] period_cnt;
always @ (posedge CLK)
begin
syn1 <= cat_in;
syn2 <= syn1;
end
assign cat_in_pos = syn1 & (~syn2);
always @ (posedge CLK)
begin
if (cat_in_pos)
period_cnt <= period_cnt + 1'b1;
if (period_cnt == 32'd5000)
begin
P_on <= P_on_reg;
P_off <= P_off_reg;
P_on_reg <= 32'b0;
P_off_reg <= 32'b0;
period_cnt <= 32'b0;
end
else if (syn1)
P_on_reg <= P_on_reg + 1'b1;
else
P_off_reg <= P_off_reg + 1'b1;
end
endmodule
\ No newline at end of file
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/01/15 14:15:26
// Design Name:
// Module Name: Freq_Counter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Freq_Counter(
input CLK,
input signal,
output [31:0] cnt1_out,
output [31:0] cnt2_out
);
wire CLK_10k;
wire pre_gate;
wire act_gate_out;
CLK_out_10k(.CLK(CLK),.CLK_10k(CLK_10k));
PreGate pre(.CLK(CLK),.gate_out(pre_gate));
ActGate act(.signal(signal),.gate_in(pre_gate),.gate_out(act_gate_out));
counter cnt1(.signal(signal),.gate(act_gate_out),.cnt_out(cnt1_out));
counter cnt2(.signal(CLK_10k),.gate(act_gate_out),.cnt_out(cnt2_out));
endmodule
module CLK_out_10k(
input CLK,
output reg CLK_10k
);
reg gate_buf;
reg [31:0] cnt;
always @ (posedge CLK)
begin
if (cnt == 32'd10000)
begin
gate_buf <= ~gate_buf;
CLK_10k <= gate_buf;
cnt <= 32'd0;
end
else
cnt <= cnt + 1'b1;
end
endmodule
module PreGate(
input CLK,
output reg gate_out
);
reg gate_buf;
reg [31:0] cnt;
always @ (posedge CLK)
begin
if (cnt == 32'd100000000)
begin
gate_buf <= ~gate_buf;
gate_out <= gate_buf;
cnt <= 32'd0;
end
else
cnt <= cnt + 1'b1;
end
endmodule
module ActGate(
input signal,
input gate_in,
output reg gate_out
);
always @ (posedge signal)
gate_out <= gate_in;
endmodule
module counter(
input signal,
input gate,
output reg [31:0] cnt_out
);
reg [31:0] cnt;
reg gate_buf;
always @ (posedge signal)
begin
if ((gate == 1'b1) && (gate_buf == 1'b0))
cnt <= 32'b1;
else if ((gate == 1'b0) && (gate_buf == 1'b1))
cnt_out <= cnt;
else if (gate_buf == 1'b1)
cnt <= cnt + 1'b1;
end
endmodule
\ No newline at end of file
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/01/15 14:15:26
// Design Name:
// Module Name: Phase_Counter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Phase_Counter_1(
input CLK,
input M,
input N,
output reg [31:0] P_on,
output reg [31:0] P_off
);
reg XOR_out;
reg syn1;
wire cat_in_pos;
reg [31:0] P_on_reg;
reg [31:0] P_off_reg;
always @ (posedge CLK)
begin
XOR_out <= M ^ N;
syn1 <= XOR_out;
end
assign cat_in_pos = XOR_out & (~syn1);
always @ (posedge CLK)
begin
if (cat_in_pos)
begin
P_on <= P_on_reg;
P_off <= P_off_reg;
P_on_reg <= 32'b0;
P_off_reg <= 32'b0;
end
else if (XOR_out)
P_on_reg <= P_on_reg + 1'b1;
else
P_off_reg <= P_off_reg + 1'b1;
end
endmodule
module Phase_Counter_2(
input CLK,
input M,
input N,
output reg [31:0] P_on,
output reg [31:0] P_off
);
reg XOR_out;
reg syn1;
wire cat_in_pos;
reg [31:0] P_on_reg;
reg [31:0] P_off_reg;
reg [31:0] phase_cnt;
always @ (posedge CLK)
begin
XOR_out <= M ^ N;
syn1 <= XOR_out;
end
assign cat_in_pos = XOR_out & (~syn1);
always @ (posedge CLK)
begin
if (cat_in_pos)
phase_cnt <= phase_cnt + 1'b1;
if (phase_cnt == 32'd2000)
begin
P_on <= P_on_reg;
P_off <= P_off_reg;
P_on_reg <= 32'b0;
P_off_reg <= 32'b0;
phase_cnt <= 32'b0;
end
else if (XOR_out)
P_on_reg <= P_on_reg + 1'b1;
else
P_off_reg <= P_off_reg + 1'b1;
end
endmodule
module Phase_Counter_3(
input CLK,
input M,
input N,
output reg [31:0] P_on,
output reg [31:0] P_off
);
reg XOR_out;
reg syn1;
wire cat_in_pos;
reg [31:0] P_on_reg;
reg [31:0] P_off_reg;
reg [31:0] phase_cnt;
always @ (posedge CLK)
begin
XOR_out <= M ^ N;
syn1 <= XOR_out;
end
assign cat_in_pos = XOR_out & (~syn1);
always @ (posedge CLK)
begin
if (cat_in_pos)
phase_cnt <= phase_cnt + 1'b1;
if (phase_cnt == 32'd20000)
begin
P_on <= P_on_reg;
P_off <= P_off_reg;
P_on_reg <= 32'b0;
P_off_reg <= 32'b0;
phase_cnt <= 32'b0;
end
else if (XOR_out)
P_on_reg <= P_on_reg + 1'b1;
else
P_off_reg <= P_off_reg + 1'b1;
end
endmodule
\ No newline at end of file
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/01/15 14:15:26
// Design Name:
// Module Name: SPI_Comm
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SPI_Comm(
input CLK,
input sCLK,
input En,
input CS,
input [35:0] Data_snd,
output reg SDO,
input SDI,
output reg [35:0] Data_rcv
);
reg snd_flag;
reg rcv_flag;
reg [35:0] snd_buf;
reg [35:0] rcv_buf;
reg [7:0] snd_step;
reg [7:0] rcv_step;
initial begin
snd_flag <= 1'b0;
rcv_flag <= 1'b1;
snd_step <= 8'b0;
rcv_step <= 8'b0;
end
always @ (posedge CLK)
begin
if (En)
begin
if (snd_flag == 0)
snd_buf <= Data_snd;
end
end
always @ (posedge CLK)
begin
if (En)
begin
if (rcv_flag == 0)
Data_rcv <= rcv_buf;
end
end
always @ (negedge sCLK or posedge CS)
begin
if (CS)
begin
snd_flag <= 1'b0;
snd_step <= 8'b0;
end
else
begin
if (En)
begin
if (snd_step < 8'd35)
begin
snd_step <= snd_step + 1'b1;
snd_flag <= 1'b1;
end
else
begin
snd_step <= 8'b0;
snd_flag <= 1'b0;
end
end
else
begin
snd_step <= 8'b0;
snd_flag <= 1'b0;
end
end
end
always @ (posedge sCLK)
begin
if (En)
if (CS == 0)
SDO <= snd_buf[35 - snd_step];
end
always @ (posedge sCLK or posedge CS)
begin
if (CS)
begin
rcv_flag <= 1'b0;
rcv_step <= 8'b0;
end
else
begin
if (En)
begin
if (rcv_step < 8'd36)
begin
rcv_step <= rcv_step + 1'b1;
rcv_flag <= 1'b1;
end
else
begin
rcv_step <= 8'b0;
rcv_flag <= 1'b0;
end
end
else
begin
rcv_step <= 8'b0;
rcv_flag <= 1'b0;
end
end
end
always @ (negedge sCLK)
begin
if (En)
begin
if (CS == 0)
rcv_buf[36 - rcv_step] <= SDI;
end
end
endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/01/15 11:15:10
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top(
input CLK,
input CS,
input sCLK,
input flag,
input signal,
input signal1,
input signal2,
output SDO
);
wire [31:0] cnt1, cnt2;
wire [31:0] duty_on, duty_off;
wire [31:0] phase1, phase2, phase3;
wire [31:0] phase, phase_flag;
wire [35:0] data_to_send;
wire [2:0] freq_high_flag_1;
wire [2:0] freq_high_flag_2;
wire [31:0] P_on_1, P_on_2, P_on_3, P_off_1, P_off_2, P_off_3;
wire [31:0] P_on, P_off;
wire [31:0] sp_result;
wire CLK_200M;
//wire CLK_300M;
Freq_Counter freq(
.CLK(CLK),
.signal(signal),
.cnt1_out(cnt1),
.cnt2_out(cnt2)
);
Freq_Counter sp_unit(
.CLK(CLK),
.signal(signal1),
.cnt1_out(sp_result)
);
Duty_Counter_1 duty_fast(
.CLK(CLK_200M),
.cat_in(signal),
.P_on(P_on_1),
.P_off(P_off_1)
);
Duty_Counter_2 duty_mid(
.CLK(CLK_200M),
.cat_in(signal),
.P_on(P_on_2),
.P_off(P_off_2)
);
Duty_Counter_3 duty_slow(